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  • Tetsuya Iizuka and Asad A. Abidi,
    "FET-R-C Circuits: A Unified Treatment—Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance",
    IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol 63, No. 9, pp. 1337-1348,2016.
  • Tetsuya Iizuka and Asad A. Abidi,
    "FET-R-C Circuits: A Unified Treatment—Part I: Signal Transfer Characteristics of a Single-Path",
    IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol 63, No. 9, pp. 1325-1336,2016.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "A 15× 15 single photon avalanche diode sensor featuring breakdown pixels extraction architecture for efficient data readout",
    Japanese Journal of Applied Physics, Vol 55, No. 4S, pp. 04EF04,2016.
  • T. Kikkawa, T. Nakura, K. Asada,
    "An on-chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface,"
    IEICE Trans. on Electronics, Vol. E99-C, No.2, pp. 275-284,Feb.2016.
  • Norihito Tohge, Tetsuya Iizuka, Toru Nakura, Satoshi Miura, Yoshimichi Murakami, and Kunihiro Asada,
    "A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique,"
    IEICE Technical Report, Vol. 115, No. 340, pp. 17-22, Dec.2015.
  • Takehisa Koga, Tetsuya Iizuka, Toru Nakura, and Kunihiro Asada,,
    "Design of Fine-Resolution Pulse Shrinking Time-to-Digital Converter,"
    IEICE Technical Report, Vol. 115, No. 270, pp. 13-18, Oct.2015.
  • Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, and Kunihiro Asada,
    "A Near-Field Magnetic Sensing System with High-Spacial Resolution and Application for Security of Cryptographic LSIs,"
    IEEE Trans. on Instrumentation & Measurement, Vol. 64, No. 4, pp.840-848,Apr.2015.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors,"
    Journal of Circuits, Systems and Computers (JSCS), Vol. 25, No. 3,(2016)1640017.
  • 池田司,池田誠,
    "汎用暗号プロセッサにおけるモンゴメリ乗算器の並列化 ,"
    2017年電子情報通信学会総合大会, Mar.2017.
  • K.Xu, T. Iizuka, T.Nakura and K. Asada,
    "High Spatial Resolution Detection Method for Point Light Source in Scintillator,"
    in Proceedings of Electronic Imaging 2017 (EI2017) Jan.2017.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    "A 15 x 15 SPAD Array Sensor with Breakdown-Pixel-Extraction Architecture for Efficient Data Readout,"
    in Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) Jan.2017.
  • 池田司,池田誠,
    "楕円曲線に基づく公開鍵暗号向け汎用暗号プロセッサの設計,"
    暗号と情報セキュリティシンポジウム(SCIS) 2017 Jan.2017.
  • Masahiro Kano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    "Fine-Resolution Light Source Position Estimation Method for Scintillation Detector,"
    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Dec.2016.
  • Tetsuya Iizuka, Takehisa Koga, Toru Nakura and Kunihiro Asada,
    "A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection Utilizing Built-in Offset Pulse,"
    in IEEE Asian Solid-State Circuits Conference (A-SSCC) Proceedings of Technical Papers, pp. 313 - 316, Nov.2016.
  • 池田司,池田誠,
    "1024bit までの有限体上の演算と256bit までの楕円曲線上の演算のための汎用暗号プロセッサ,"
    電子情報通信学会ハードウェアセキュリティフォーラム2016 Dec.2016.
  • Xiao Yang, Toru Nakura, Tetsuya Iizuka, and Kunihiro Asada,
    "A 31x31 SPAD Array Sensor with Variable Readout Time for Scintillation Light Detection,"
    in IEICE Society Conference 2016, C-12-11, Sep.2016.
  • T. Ikeda, M. Ikeda ,
    "Scalable Processor Design for Cryptography on Finite Field and Elliptic Curve,"
    in IEICE Society Conference 2016, A-7-5, Sep.2016.
  • Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, and Kunihiro Asada,
    "Microwave Pulse Generator based on Current-Mode Trigger and On-Quartz Transmission Line,"
    in IEICE Society Conference 2016, C-2-26, Sep.2016.
  • Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura and Kunihiro Asada,
    "A 4-Cycle-Start-Up Reference-Clock-Less All-Digital Burst-Mode CDR Based on Cycle-Lock Gated-Oscillator with Frequency Tracking,"
    in Proceedings of IEEE European Solid-State Circuits Conference (ESSCIRC), Sep.2016.
  • Parit Kanjanavirojkul and Kunihiro Asada,
    "A CMOS-on-Quartz Pulse Generator for Low Power Applications,"
    VDECデザイナーズフォーラム2016, Aug.2016, (VDEC デザインアワード奨励賞).
  • Takahiro Yamaguchi, Katsuhiko Degawa, Tetsuya Iizuka and Kunihiro Asada,
    "Common Pitfalls in Application of a Threshold Detection Comparator to a Continuous-Time Level Crossing Quantization,"
    in Proceedings of IEEE International Mixed-Signal Testing Workshop (IMSTW), Jul.2016.
  • P. Kanjanavirojkul, N.N.M Khanh, T. Iizuka, T. Nakura, K. Asada,
    "Analysis and Implementation of Quick-Start Pulse Generator by CMOS Flipped on Quartz Substrate,"
    in Proceeding of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, May.2016.
  • Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, and Kunihiro Asada,
    "A Damping Pulse Generator based on Regenerated Trigger Switch,"
    in Proceeding of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.11-14 May.2016.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "A 15× 15 SPAD sensor featuring breakdown pixels extraction architecture for efficient data readout,"
    LSI and Systems Workshop,May.2016.
  • Tetsuya Iizuka and Asad A. Abidi,
    "Sampling Circuits: Unified treatment of S/H, mixer, and sampling oscilloscope front-ends,"
    Tutorial Course in IEEE International Conference on Microelectronic Test Structures (ICMTS), Mar.2016.
  • P. Kanjanavirojkul, N.N.M Khanh, T. Iizuka, T. Nakura, K. Asada,
    "An X-band CMOS-on-Quartz Pulse Generator for Low Power Applications,"
    in Proceedings of the 2016 IEICE General Conference,C-12-7, May.2016.
  • T. Ikeda, M. Ikeda,
    "Accelation of Operation on Elliptic Curve by Parallelized High-Radix Arithmetic Unit(高基数演算器の並列化による楕円曲線上の演算の高速化の検討),"
    in Proceedings of the 2016 IEICE General Conference,A-6-8,Mar.2016.
  • K.Xu, T. Iizuka, T.Nakura and K. Asada, ,
    "Resonant Power Supply Noise Reduction Using a Triangular Active Charge Injection,"
    in Proceedings of IEICE General Conference 2016 Mar.2016.
  • Masahiro Kano, Toru Nakura and Kunihiro Asada,
    "Analysis and Design of a Triangular Active Charge Injection for Stabilizing Resonant Power Supply Noise,"
    17th International Symposium on Quality Electronic Design (ISQED), Mar.2016.
  • Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada,
    "Analytical Design Optimization of Sub-ranging ADC Based on Stochastic Comparator,"
    IEEE/ACM Design, Automation and Test in Europe (DATE) Exhibition and Conference, Mar.2016.
  • Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada,
    “Performance Analysis of Analog to Digital Converter based on Stochastic Comparator(統計的コンパレータを用いたアナログ‐ディジタル変換回路の性能解析),"
    IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
  • Tomohiko Yano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    “A Time-Mode Analog Signal Accumulator Using a Single Buffer Ring without Output Drift Calibration(バッファリングを利用した出力ドリフト補正が不要な時間領域 アナログ信号積分器),"
    IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
  • Takashi Toi, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    “Hill-Climbing法を用いたパルス幅制御PLLのPVTばらつきへの自動適応,"
    IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
  • Tomohiko Yano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    "A Calibration-Free Time Difference Accumulator Using Two Pulses Propagating on a Single Buffer Ring,"
    in IEEE Asian Solid-State Circuits Conference (A-SSCC) Proceedings of Technical Papers, pp. 145-148,Nov.2015.
  • T. Ikeda, M. Ikeda,
    "Comprehensive Study on Higher Order Radix RSA Cryptography Engine,"
    in Proceedings of the IEEE 11th International Conference on ASIC (ASICON), P2-72,Nov.2015.
  • Takashi Toi, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
    "Tracking PVT variations of Pulse Width Controlled PLL using Variable-Length Ring Oscillator,"
    in Proceedings of IEEE Nordic Circuits and Systems Conference(NORCAS),Oct.2015.
  • T. Ikeda, M. Ikeda,
    "Implementation of RSA Cryptographic Circuit with High Radix Arithmetic Unit and Asynchronous Control(高基数演算器を用いたRSA暗号回路の非同期制御による実装),"
    in Proceedings of the 2015 IEICE Society Conference, A-3-12,Sep.2015.
  • Chuanqi Cui, M. Ikeda,
    "Evaluation of SEU Tolerance of Self-synchronous System Based on Dynamic Circuits(ダイナミック回路を用いた自己同期システムの SEU 耐性の評),"
    in Proceedings of the IEICE Society Conference, A-3-9,Sep.2015.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "A CMOS SPAD Sensor Featuring Asynchronous Event-Extraction Readout Architecture for Faint Light Detection,"
    in Proceedings of 2015 International Conference on Solid State Devices and Materials (SSDM), pp. 812-813,Sep.2015.
  • M. Kano, T. Nakura and K. Asada,
    "Resonant Power Supply Noise Cancelling with Noise Detector based in DLL and Vernier TDC,"
    in Proceedings of IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.192-196,Aug.2015.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors,"
    in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 131-136,Apr.2015.
  • Xiao Yang, Hongbo Zhu, Toru Nakura, Kunihiro Asada,
    "Single Photon Avalanche Diode Based on Standard CMOS Technology(標準CMOS技術による単一光子アバランシェフォトダイオード),"
    in Proceedings of the 2015 IEICE General Conference, C-12-39,Mar.2015.
  • K. Mori, T. Nakura, T. Iizuka, and K. Asada,
    "An Accelerating Method of NBTI Degradation Transition Analysis Utilizing its Frequency Dependence(NBTIの周波数依存性を利用した劣化過渡解析の高速 化手法),"
    in Proceedings of the 2015 IEICE General Conference, A-2-29,Mar.2015.
  • Chuanqi Cui, M. Ikeda,
    "Layout Area Estimation for Evaluation of SEU Tolerance(SEU耐性評価のためのレイアウト面積の概算),"
    in Proceedings of the IEICE General Conference, C-12-25,Mar.2015.
  • Nguyen Ngoc Mai-Khanh, Tetsuya IIZUKA, Shigeru NAKAJIMA, and Kunihiro ASADA,
    "Spacial Resolution Enhancement of Integrated Magnetic Probe by Two-Step Removal of Si-Substrate Beneath the Coil,"
    IEEE Trans. on Magnetics Vol. 51, No. 1,Jan.2015.
  • Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, and Kunihiro Asada,
    "A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing,"
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,vol. E97-A, no. 8, pp. 1688 - 1698,Aug. 2014.
  • K. Mori, T. Nakura, T. Iizuka, and K. Asada,
    "An accelerating method of NBTI degradation transition analysis based on logic simulation(論理シミュレーションにもとづいたNBTI劣化過渡解 析の高速化手法),"
    ICD2014-109,CPSY2014-121, pp.141-145, Dec. 2014.
  • N. N. Mai-Khanh, T. Iizuka, S. Nakajima, and K. Asada,
    "Spacial Resolution Enhancement for Integrated Magnetic Probe by Two-Step Removal of Si-Substrate Beneath the Coil,"
    in 10th European Conference on Magnetic Sensors and Actuators (EMSA), Vienna, Austria, pp. 11, Jul. 2014.
  • Chuanqi Cui, M. Ikeda,
    "Error Tolerance of Dual Pipeline Self Synchronous Circuits(ゲートレベルパイプライン型自己同期回路のエラー耐性の評価),"
    電子情報通信学会VLSI設計研究会,信学技報, vol. 114, no. 59, VLD2014-7, pp. 33-38, May 2014.
  • Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, and Kunihiro Asada,
    "High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-dimensional VIA Characters,"
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences,vol. E96-A, no. 12, pp. 2458 - 2466,Dec. 2013.
  • Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Makoto Yamada, Osamu Morita, and Kunihiro Asada,
    "An Integrated High-Precision Probe System in 0.18-um CMOS for Near-Field Magnetic Measurements on Cryptographic LSIs,"
    IEEE Sensors Journal, vol. 13, no. 7, pp. 2675 - 2682, Jul. 2013.
  • N. N. Mai-Khanh, T. Iizuka, A. Sasaki, M. Yamada, O. Morita, and K. Asada,
    "High-Resolution Measurement of Magnetic Field Generated from Cryptographic LSIs,"
    in Proceedings of IEEE Sensors Applications Symposium (SAS), Feb. 2014.
  • T. Yano, T. Nakura, and K. Asada,
    "Low Pass Filter-less Pulse Width Controlled PLL with Zero Phase Offset Using Pulse Width Accumulator,"
    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 625-628, Dec. 2013.
  • Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, and Kunihiro Asada,
    "A True 4-Cycle Lock Reference-Less All-Digital Burst-Mode CDR Utilizing Coarse-Fine Phase Generator with Embedded TDC,"
    in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
  • Tetsuya Iizuka, Teruki Someya, Toru Nakura, and Kunihiro Asada,
    "An All-Digital Time Difference Hold-and-Replication Circuit utilizing a Dual Pulse Ring Oscillator,"
    in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2013.
  • H. Yabe, M. Ikead,
    "A CMOS Image Sensor for In-Pixel Background Suppression and Frequency and Phase Detection for Structured Light 3-D Acquisition Systems,"
    in Proceedings of the 2013 International Image Sensor Workshop, pp.341-344, Jun. 2013.
  • T. Matsushima, M. Ikead,
    "CMOS Image Sensor for 3-D Range Map Acquisition With Pixel-Parallel Correlation In Region of Interest,"
    in Proceedings of the 2013 International Image Sensor Workshop, pp.353-356, Jun. 2013.
  • Atsushi Shimada, Hongbo Zhu, and Tadashi Shibata,
    "A VLSI DBSCAN Processor Composed As an Array of Micro Agents Having Self-Growing Interconnects,"
    in the Proceedings of 2013 International Symposium on Circuits and Systems (ISCAS'13), pp. 2062~2065, May. 2013.
  • Pushe Zhao, Hongbo Zhu, and Tadashi Shibata,
    "A Multiple-Candidate-Regeneration-Based Object Tracking System with Enhanced Learning Capability by Nearest Neighbor Classifier,"
    in the Proceedings of 2013 International Symposium on Circuits and Systems (ISCAS'13), pp. 2392~2395, May. 2013.
  • H.Yabe and M.Ikeda,
    "Line Position Detection Using Minimum Voltage Circuits on the Pixel Plane,"
    in IEICE General Conference,C-12-15, Mar.2014
  • P. Kanjanavirojkul, N.N.M Khanh, K. Asada,
    "Direct Burst Pulse Generator for Sub-millimeter Wave Integrated on 65-nm CMOS,"
    in Proceedings of the 2013 IEICE Society Conference,C-2-15, Sep. 2013.
  • H. Matsui, T. Nakura, and K. Asada,
    "A Rectifier with Body Bias Effets for Radio Wave Energy Harvesting,"
    in Proceedings of the 2013 IEICE Society Conference, pp.69, Sep. 2013.
  • Muriithi Kevin Ngari, Tetsuya Iizuka, Toru Nakura, Kunihiro Asad,
    "Effect of CMOS Device Scaling on Time-domain and Voltage-domain Dynamic Range,"
    in Proceedings of the 2013 IEICE Society Conference, C-12-40, pp.100, Sep. 2013.
  • S. Bushnaq, M. Ikeda, K. Asada
    "All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences Vol.E95-A No.12 pp.2234-2241 Dec. 2012.
  • Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada
    "Frequency Resolution Enhancement for Digitally-Controlled Oscillator based on a Single-Period Switching Scheme"
    IEICE Trans. on Electronics, Vol. E95-C, No.12, pp. 1857-1863,Dec. 2012.
  • H. Yabe, M. Ikeda
    "A study on improving modulated light detection performance in the presence of background light, (ロバストな3次元取得システムのためのCMOSイメージセンサの設計)"
    映情学技報 vol. 36, no. 38, IST2012-43, Sep. 2012.
  • Nguyen Ngoc Mai-Khanh, Masahiro SASAKI, and Kuhiniro ASADA,
    "A Millimeter-Wave Resistor-less Pulse Generator with a New Dipole-Patch Antenna in 65-nm CMOS,"
    Springer Analog Integrated Circuits and Signal Processing, Vol.73 Issue 3 pp.789-799 Jul. 2012.
  • B. Devlin, M. Ikeda, K. Asada,
    "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling,"
    IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 546-554,Apr. 2012.
  • T. Iizuka, S. Miura, R. Yamamoto, Y. Chiba, S. Kubo, K. Asada
    "580fs-Resolution Time-to-Digital Converter utilizing Differential Pulse-Shrinking Buffer Ring in 0.18um CMOS Technology,"
    IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 661-667,Apr. 2012.
  • T. Iizuka, K. Asada
    "All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
    IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 627-634,Apr. 2012.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, K. Asada,
    "On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction,"
    IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 643-650,Apr. 2012.
  • H. Yabe, M. Ikeda
    "3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern,"
    IEICE Trans. on Electronics, Vol. E95-C, No.4, pp. 635-642,Apr. 2012.
  • Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    "A Structured Routing Architecture and its Design Methodology Suitable for High-throughput Electron Beam Direct Writing with Character Projection,"
    in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 69 - 76, Mar. 2013.
  • Takashi Maruyama, Hiroshi Takita, Rimon Ikeno, Morimi Osawa, Yoshinori Kojima, Shinji Sugatani, Hiromi Hoshino, Toshio Hino, Masaru Ito, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    "Practical Proof of CP Element Based Design for 14nm Node and Beyond,"
    in Proceedings of the SPIE Advanced Lithography (Alternative Lithographic Technologies V), Vol. 8680, Feb. 2013.
  • Nguyen Ngoc Mai-Khanh and Kunihiro Asada,
    "A CMOS Fully Integrated Antenna System Transceiver with Beam-formability for Millimeter-wave Active Imaging,"
    in Proceedings of IEEE 13th Silicon Monilithic Integrated Circuit in RF Systems (SiRF), paper 123 - 125 Jan. 2013.
  • Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada,
    "High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection using Character Sets Based on One-dimensional VIA Arrays with Area-efficient Stencil Design,"
    in Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), pp.255-260, Jan. 2013.
  • Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, and Kunihiro Asada,
    "Power Integrity Control of ATE for Emulating Power Supply Fluctuations on Customer Environment,"
    in Proceedings of IEEE International Test Conference (ITC), paper 7.3, Nov. 2012.
  • Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
    "Impact of All-Digital PLL on SoC Testing,"
    in Proceedings of the 21st IEEE Asian Test Symposium (ATS), pp. 252-257, Nov. 2012.
  • Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Makoto Yamada, Osamu Morita, Kunihiro Asada,
    "An Integrated High-Precision Probe System for Near-Field Magnetic Measurements on Cryptographic LSIs,"
    in Proceedings of IEEE Sensors 2012, pp. 2074-2077, Oct. 2012.
  • Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada,
    "7.5Vmax Arbitrary Waveform Generator with 65nm Standard CMOS under 1.2V Supply Voltage,"
    in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2012.
  • Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,
    "Review and Future Prospects on Time-Domain Analog Approach,"
    The second Solid-State Systems Symposium 2012 (4S-2012), Aug. 2012.
  • Makoto Ikeda, Tetsuya Iizuka, Satoshi Komatsu, Masahiro Sasaki, Toru Nakura, and Kunihiro Asada,
    "Intelligent-PAD2.0: Platform for On-line SoC Health Condition Monitoring,"
    European Workshop on Microelectronics Education (EWME), May. 2012.
  • Takashi Maruyama, Yasuhide Machida, Shinji Sugatani, Hiroshi Takita, Hiromi Hoshino, Toshio Hino, Masaru Ito, Akio Yamada, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada,
    "CP Element Based Design for 14nm Node EBDW High Volume Manufacturing,"
    in Proceedings of the SPIE Advanced Lithography (Alternative Lithographic Technologies IV), Vol. 8323, Paper 8323-39, Feb. 2012.
  • B. Devlin, M. Ikeda, K. Asada
    "A Self Synchronous FPGA with Leakage Control for 270mV Sub-threshold Operation,"
    IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems (MSCAS) 2012, Nov. 2012.
  • B. Devlin, H. Mori, S. Miyauchi, M. Ikeda, K. Asada
    "Performance and Side-channel Attack Analysis of a Self Synchronous Montgomery Multiplier Processing Element for RSA in 40nm CMOS"
    Asian Solid-State Circuits Conference (A-SSCC) 2012, pp. 385-388, 12-14, Nov. 2012.
  • K. Kodama and M. Ikeda,
    "Target Voltage Independent Capacitance Measurement Circuit Implemented by 0.18 um CMOS for PWM-MEMS Control"
    IEEE International SoC Design Conference (ISOCC), pp. 77-80, Jeju, Korea, Nov. 2012.
  • B. Devlin, M. Ikeda, and K. Asada,
    "Gate-level Process Variation Offset Technique by using Dual Voltage Supplies to Achieve Near-threshold Energy Efficient Operation,"
    IEEE Symposium on Low-Power and High-Speed Chips (COOL chips XV), Yokohama, Japan, Apr. 2012.
  • T.-W. Chen and M. Ikeda,
    "A Millimeter-Wave Resistor-less Pluse Generator with a New Diple-Patch Antenna in 65-nm CMOS,"
    IEEE Symposium on Low-Power and High-Speed Chips (COOL chips XV), Yokohama, Japan, Apr. 2012.
  • Hiroki Yabe, Makoto Ikeda,
    " Measurement of a Pulse Frequency Modulator for Correlation Image Sensor (検波型イメージセンサに向けたパルス周波数変調回路の測定),"
    IEICE General Conference 2013, C-12-5 Mar. 2013.
  • T. Kubota, T. Nakura, T. Iizuka, K. Asada,
    "Observation of Ray Tracing in the Scintillator Utilizing Single Photon Avalanche Diode Arrays,(単一光子アバランシェダイオードアレイを用いたシンチレータ内の発光軌跡観測,)"
    IEICE General Conference 2013, C-1-18, p.18, Mar. 2013.
  • So Saito, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, and Kunihiro Asada,
    "Resonant Noise Reduction of DVS Using Active Charge Sharing,"
    STARC Symposium 2013, Student Poster Session, Jan. 2013.
  • Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    "Interconnect Design and Character Extraction Method for Throughput Enhancement and Stencil Area Reduction of VIA Layer Exposure for Electron Beam Direct Writing with Character Projection Technique,"
    in Proceedings of IPSJ DA Symposium 2012,Aug 2012.
  • S. Saito, T. Nakura, T. Iizuka, K. Asada,
    "Resonant Supply Noise Reduction Using Active Charge Sharing of Dynamic Voltage Scaling"
    in Proc. of IEICE Society Conference, C-12-41, p. 114,Sep. 2012.
  • K. Kodama, T. Iizuka, T. Nakura, K. Asada,
    "Frequency Resolution Enhancement for Digitally-Controlled Oscillator based on a Single-Period Switching Scheme"
    The Workshop about LSI and Systems 2012, Kokura, Japan, May 2012.
  • T. Nakura, K. Asada,
    "Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter,"
    IEICE Trans. on Electronics, Vol. E95-C, No.2, pp. 297-302,Mar. 2012.
  • N. N. Mai Khanh, M. Sasaki and K. Asada,
    "A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application,"
    IEICE Trans. on Electronics, Vol. E94-A, No.12, pp. 2554-2562,Dec. 2011.
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation,"
    AICIT Journal of Next Generation Information Technology, Vol. 2, No. 4, pp. 1-9,Nov. 2011.(invited)
  • N. N. Mai Khanh, M. Sasaki and K. Asada,
    "A 0.25-um Si-Ge Fully Integrated Pulse Transmitter with On-chip Loop Antenna Array towards Beam- Formability for Millimeter-Wave Active Imaging,"
    IEICE Trans. on Electronics, Vol. E94-C, No.10, pp. 1626-1633Oct. 2011.
  • B. Devlin, M. Ikeda, and K. Asada
    "A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation ,"
    IEEE Journal of Solid-State Circuits, Vol. 46, No.11, pp. 2500-2513,Oct. 2011.
  • S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
    "1.0ps Resolution Time-to-Digital Converter based on Cascaded Time-Difference-Amplifier utilizing Differential Logic Delay Cells,"
    IEICE Trans. on Electronics, Vol. E94-C, No.6, pp. 1098-1104,Jun. 2011.
  • S. Mandai, T. Nakura, T. Iizuka, M. Ikeda, and K. Asada,
    "Cascaded Time Difference Amplifier With Differential Logic Delay Cell,"
    IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 654-662,Apr. 2011.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
    "On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch,"
    IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 511-519,Apr. 2011.
  • T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
    "All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter,"
    IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 487-494,Apr. 2011.
  • B. Devlin, M. Ikeda, and K. Asada,
    "Gate-Level Autonomous Watchdog Circuit for Error Robustness Based on a 65nm Self Synchronous System,"
    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 53-57,Dec. 2011.
  • S. Bushnaq, M. Ikeda, and K. Asada.,
    "All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS,"
    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 607-610,Dec. 2011.
  • K. Asada,
    "Solutions for Side Effect of Low Voltage Operation in Deep Sub‐micron VLSI Circuits,"
    Plenary Talk in IEEE International SoC Design Conference 2011, Nov. 2011.
  • T. Nakasato, T. Nakura, and K. Asada,
    "Stress-Balance Flip-Flops for NBTI Tolerant Circuit based on Fine-Grain Redundancy,"
    in Proceedings of IEEE International SoC Design Conference (ISOCC), pp.150-153, Nov. 2011.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada
    "On-Chip Resonant Supply Noise Reduction Utilizing Switched Parasitic Capacitors of Sleep Blocks with Tri-Mode Power Gating Structure"
    in Proceedings of IEEE European Solid-State Circuit Conference (ESSCIRC), pp.183-186, Sep. 2011,
  • K. Kodama, T. Iizuka, and K. Asada,
    "A High Frequency Resolution Digitally Controlled Oscillator Using Single-Period Switching Scheme"
    in Proceedings of IEEE European Solid-State Circuit Conference (ESSCIRC), pp.399-402, Sep. 2011,
  • B.S. Devlin, M. Ikeda, and K. Asada,
    "Energy Minimum Operation in a Reconfigurable Gate-level Pipelined and Power-Gated Self Synchronous FPGA,"
    in Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, Aug. 2011.
  • N.N.M. Khanh, M. Sasaki, and K. Asada
    "A Millimeter-Wave Resistor-less Pluse Generator with a New Diple-Patch Antenna in 65-nm CMOS,"
    IEEE International NEWCAS conference, Jun. 2011.
  • H. Yabe, and M. Ikeda
    "CMOS Image Sensor for 3-D range map acquisition Using Time Encoded 2-D Structured Pattern,"
    International Image Sensor Workshop, Hokkaido, Japan, Jun. 2011,
  • T. Kikkawa, T. Nakura, and K. Asada
    "An Automatic Phase Control Circuit with DLL-like Architecture for Phased Array Antenna Systems"
    Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, Sep. 2011.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
    "Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction,"
    in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 111-114, Apr. 2011.
  • T. Iizuka and K. Asada,
    "An All-Digital On-Chip PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
    in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 115-120, Apr. 2011.
  • X. Fu, M. Ikeda
    "Evaluation of Background Light Suppression Characteristic and Range Finding Accuracy for 3-D Measurement using Smart Imgae Sensor,"
    ITE Technical Report, Vol. 36, No. 18, pp. 27-30,Mar. 2012.
  • K.Kodama and M. Ikeda
    "High-Voltage Capacitance Measurement Circuit for MEMS-Integrated LSI",
    IEICE Technical Report, vol. 111, no. 497, pp. 7-12,Mar. 2012 .
  • T. W. Chen and M. Ikeda
    "Analysis of On-Line Clustering Algorithm for Low-Power Hardware Implementation,"
    IEICE General Conference 2012, D-6-4,Mar. 2012 .
  • T. Kikkawa, T. Nakura, K. Asada
    "An Effect of Variability to RF Circuits for Phased Array Systems,"
    IEICE General Conference 2012, C-12-71,Mar. 2012 , (in Japanese).
  • H. Yabe and M. Ikeda
    "A study on improving modulated light detection performance in the presence of background light,"
    IEICE General Conference 2012, C-12-34,Mar. 2012 .
  • T. Kikkawa, T. Nakura, K. Asada
    "An Automatic Phase Control Circuit for Phased Array Antenna Systems"
    IEICE Society Conference, C-12-28, p. 103, Sep. 2011 , (in Japanese).
  • H. Yabe, M. Ikeda
    "3-D Range Map Acquisition System Based on CMOS Image Sensor"
    Technical Group on Information Sensing Technologies, Sep. 2011 , (in Japanese).
  • T. Iizuka and K. Asada,
    "All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
    IEICE Technical Report, vol. 111, no. 151, pp. 63-68,Jul. 2011.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
    "On-Chip Resonant Supply Noise Reduction Using Active Decoupling Capacitors,"
    IEICE Technical Report, vol. 111, no. 151, pp. 69-72,Jul. 2011.
  • N. N. Mai Khanh, Masahiro SASAKI, and Kunihiro ASADA
    "A Millimeter-wave Resistorless Pulse Generator with a New On-chip Dipole Patch Antenna in 65-nm CMOS,"
    the 9th IEEE NEWCAS, France, The 3rd place of Best Student Paper Award, Sep. 2011.
  • T. Kikkawa, T. Nakura, and K. Asada
    "An Automatic Phase Control Circuit with DLL-like Architecture for Phased Array Antenna Systems"
    Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, Best Paper Award Sep. 2011.
  • S. Mandai, T. Momma, M. Ikeda, and K. Asada,
    "Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method,"
    IEICE Trans. On Electronics, Vol. E94-C, No.1, pp. 124-127,Jan. 2011.
  • S. Ergun, U. Guler, and K. Asada,
    "A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform,"
    IEICE Trans. On Electronics, Vol. E94-A No.1  pp.180-190,Jan. 2011.
  • T. Iizuka and K. Asada,
    "All-Digital Ramp Waveform Generator for Two-Step Single-Slope ADC,"
    IEICE Electronics Express, vol. 8, no.1, pp. 20-25 Jan. 2011.
  • S. Mandai, T. Nakura, M. Ikeda, and K. Asada,
    "A 8bit Two Stage Time-to-Digital Converter using Time Difference Amplifier,"
    IEICE Electronics Express, vol. 7, no.13, pp. 943-948 Jul. 2010.
  • B.S. Delvin, T. Nakura, M. Ikeda, and K. Asada,
    "A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment,"
    IEICE Trans. On Electronics,Vol. E93-A, pp. 1319-1328,Jul. 2010.
  • M. Ikeda,
    "PVT and Aging Torelant Systems Employing Self-Synchronous Operation,"
    Symposium LAAS/University of Tokyo GCOE Program : Secure Life Electronics, Mar. 2011.
  • N.N.M. Khanh, M. Sasaki and K. Asada,
    "A Fully Integrated Shock Wave Trasmitter with an On-chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS,"
    University Design Contest, 16th Asian and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Japan, pp. 107-108,Jan. 2011.
  • J. Jeong, T. Iizuka, T. Nakura, M. Ikeda and K. Asada,
    "All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter,"
    in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 79-80,Jan. 2011.
  • B.S. Devlin, M. Ikeda, and K. Asada,
    "A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS,"
    in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 25-28, Jan. 2011.
  • N.N.M. Khanh, M. Sasaki and K. Asada,
    "Integrated Wideband Dipole Antenna for Pulse Beam-Fomability by Using 0.18μm CMOS Technology,"
    Asia-Pacific Microwave Conference (APMC), Yokohama, Japan, pp. 1561-1564,Dec. 2010.
  • J. Jeong, T. Iizuka, T. Nakura, M. ikeda and K. Asada,
    "A Robust Pulse Delay Circuit Utilizing a Differential Buffer Ring,"
    in Proceedings of International SoC Design Conference (ISOCC), pp. 272-275Nov. 2010.
  • M. Ikeda,
    "[Plenary Talk] Dependable System against PVT and Aging Employing Self-Synchronous Operation,"
    ISOCC 2010, Nov. 2010.
  • T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
    "Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement,"
    IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, USA,Nov. 2010.
  • M. Sasaki, N.N.M. Khanh, and Kunihiro Asada,
    "A Circuit for on-Chip Skew Adjustment with Jitter and Setup Time Measurement,"
    2010 IEEE Asian Solid-State Circuits Conference (ASSCC), Beijing, China, Nov. 2010.
  • B.S. Devlin, M. Ikeda, and K. Asada,
    "A 65nm 2.97GHz Self Synchronous FPGA with 42% Power Bounce Tolerance,"
    in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 8-10, Nov. 2010.
  • M. Ikeda, and Y. Kim,
    "Measurement and Analysis on Characteristics of Transmission and Polarization for 12ML 65nm CMOS,"
    IEEE Sensors, pp. 548-551, Nov. 2010.
  • T. Nakura,
    "Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Block,"
    in Proceedings of 10th Taiwan-Japan Microelectronics Symposium,Oct. 2010.
  • K. Asada, M. Ikeda, B.S. Devlin, and T. Sogabe,
    "[Keynote] Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging,"
    25th International Symposium on, pp.3, 6-8,Oct. 2010.
  • N.N.M. Khanh, M. Sasaki, and K. Asada,
    "A 0.25-μm SiGe Millimeter-wave Damping Pulse Transmitter Chip with On-chip Loop Antenna Array,"
    the 35th IRMMW-THz 2010, Roma, Italia, Sep. 2010.
  • T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
    "All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement Utilizing Buffer Ring with Pulse Counter,"
    IEEE European Solid-State Circuits Conference, Sevilla, Spain, pp. 182-185,Sep. 2010.
  • J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
    "Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks,"
    in Proceedings of IEEE/JSAP Symposium on VLSI Circuit, pp. 119-120,Jun. 2010.
  • B.S. Devlin, M. Ikeda, and Kunihiro Asada,
    "Evaluation on the Reliable Operation of a Gate-Level Pipelined Self Synchronous System Against PVT and Aging,"
    International Integrated Reliability Workshop 2010,Oct. 2010.
  • S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
    "Time-to-Digital Converter Based on Time Difference Amplifier with Non-Linearity Calibration,"
    IEEE European Solid-State Circuits Conference, Sevilla, Spain, pp. 266-269,Sep. 2010.
  • J. Kim, T.Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
    "On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores Utilizing Parasitic Capacitance of Sleep Blocks,"
    IEICE Technical Report, vol. 110, no. 182, pp. 1-4, Aug. 2010.
  • Y. Tamaki, T. Nakura, M.Ikeda and K. Asada,
    "A Toggle-Type Peak Hold Circuit for Local Power Supply Noise Detection,"
    IEEE The Asia Symposium on Quality Electronic Design, Penang, Malaysia, pp.29-32,Aug. 2010.
  • N.N.M. Khanh, M. Sasaki, K. Asada and T. Monma,
    "A 0.18-μm CMOS Millimeter Wave Pulse Generator with Onchip Antenna and Digitally Programmable Timed Delay Circuit,"
    Asia Symposium on Quality Electronic Design (ASQED), Penang, Malaysia, Aug. 2010.
  • N.N.M. Khanh, M. Sasaki and K. Asada,
    "A CMOS Pulse Beamforming Transmitter Design with On-chip Antenna Array for Millimeter-wave Imaging Applications,"
    The 5th International Conf. on Future Information Technology (FutureTech2010), Busan, Korea, May. 2010.
  • T. Iizuka, T. Nakura, and K. Asada,
    "Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability and Aging Effects,"
    IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria, pp.167-172,Apr. 2010.
  • K. Hattori, K. Asada, and M. Ikeda,
    "Hardware design for Real-time 3D Mesh Generation,"
    ITE Technical Report, vol. 62, pp. 57-60,Oct. 2010.
  • M. Ikeda,
    "Analysis on Characteristics of Light Transmission for Multiple-metal Layer Nano-meter CMOS,"
    ITE Technical Report, vol. 45, pp. 21-24,Sep. 2010.
  • J. Jeong, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
    "Characterization of Reduced-area All Digital Process Variability Monitor,"
    電子情報通信学会 ソサイエティ大会論文集, C-12-23, p. 84,Sep. 2010.
  • J. Kim, T. Nakura, H. Takada, K. Ishibashi, M. Ikeda, and K. Asada,
    "On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores Utilizing Parasitic Capacitance of Sleep Block,"
    IEICE Technical Report, vol. 110, no. 182, pp. 1-4,Jul. 2010.
  • T. Iizuka, T. Nakura, and K. Asada,
    "Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect,"
    IEICE Technical Report, vol. 110, no. 140, pp. 15-20,Jul. 2010.
  • X. Song, K. Kim, M. Sasaki, and M. Ikeda,
    "Skewed Pixel Arrays Optical Position Sensor for High Accuracy,"
    ITE Technical Report, vol. 23, pp. 5-8,May. 2010,
  • T. Nakura
    "Time difference amplifier, from getting idea to presenting at a conference,"
    電子情報通信学会研究報告集積回路研究会, ICD2010-117, pp. 107-111,Dec.2010,
  • Nguyen Ngoc Mai Khanh, M. Sasaki, K. Asada and T. Monma,
    "A 0.18-μm CMOS Millimeter Wave Pulse Generator with Onchip Antenna and Digitally Programmable Timed Delay Circuit,"
    Asia Symposium on Quality Electronic Design (ASQED), Penang, Malaysia, Best Paper Award, Aug. 2010,
  • T. Nakura, S. Mandai, M. Ikeda, and K. Asada,
    "Time Difference Amplifier with Robust Gain Using Closed-Loop Control,"
    IEICE Trans. on Electronics, Vol. E93-C, No. 3, pp. 303-308, Mar. 2010,
  • S. Mandai, T. Nakura , M. Ikeda , K. Asada,
    "Dual Imager Core Chip with 24.8 rangemap/s 3-D and 58 fps 2-D Simultaneous Capture Capability,"
    IEICE Trans. on Electronics, Vol. E92-C, No.6, Jun. 2009,
  • T. Iizuka, D. Nakamura, H. Yoshida, S. Komatsu, M. Sasaki, M. Ikeda, and K. Asada,
    "An SoC Platform with On-Chip Web Interface for In-Field Monitoring,"
    IEEE International SoC Design Conference, Pusan, Korea, pp.208-211,Nov. 2009,
  • S. Mandai, T. Nakura, M. Ikeda, and K. Asada,
    "Cascaded Time Difference Amplifier using Differential Logic Delay Cell,"
    IEEE International SoC Design Conference, Pusan, Korea, pp.194-197,Nov. 2009,
  • S. Bushnaq, T. Nakura, M. Ikeda, K. Asada,
    "All Digital Wireless Transceiver Using Modified BPSK and 2/3 Sub-sampling Technique,"
    IEEE International Conference on ASIC, Changsha, China, Oct. 2009,
  • S. Bushnaq, T. Nakura, M. Ikeda, K. Asada,
    "All Digital Baseband 50 Mbps Data Recovery Using 5x Oversampling With 0.9 Data Unit Interval Clock Jitter Tolerance,"
    IEEE Design and Diagnostics of Electrical Circuits and Systems, Czech Republic, Apr. 2009,
  • S. Mandai, T. Nakura, M. Ikeda, and K. Asada,
    "Ultra High Speed 3-D Image Sensor,"
    International Image Sensor Workshop, Bergen, Norway, Jun. 2009,
  • T. Nakura, S. Mandai, M. Ikeda, K. Asada,
    " Study on Time Difference Amplifier Using Feedback Control,"
    CD2009-46, pp.69-74,, Oct. 2009 , (in Japanese).
  • S. Mandai, T. Nakura , M. Ikeda, K. Asada,
    " Multi Functional Dual Imager Core Chip,"
    LSI and Systems Workshop, May 2009 , (in Japanese).
  • S. Mandai, T. Nakura , M. Ikeda, K. Asada,
    " HIgh Resolution Time to Digital Converter using Time Difference Amplifier,"
    IEICE Society Conference, Sep. 2009 , (in Japanese).
  • M. Sasaki, M. Ikeda and K. Asada,
    “A Temperature Sensor With an Inaccuracy of -1/+0.8℃ Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits,”
    IEEE Transactions,Vol.21, Issue 2, pp.201-208, 2008,
  • Y. Yachide , M. Ikeda, and K. Asada,
    "Multiple-Rangefinders Calibration Based on Light-Section Method Using Spheres,"
    Smart Sensors and Sensing Technology, Springer Berlin Heidelberg, Part IX, pp. 285-298, Jul. 2008,
  • J. Kim, K. ikai, T. Nakura, M. Ikeda, K. Asada,
    "Variation Tolerant Transceiver Design for System -on- Glass,"
    in IEEE 34th European Solid State Circuits Conference (Fringe Section), Sep. 2008,
  • K. Ikai, J. Kim, M. Ikeda and K. Asada,
    "Circuit Design Using Stripe-Shaped PMELA TFTs on Glass,"
    Asia and South Pacific Design Automation Conference, pp. 105--106, Jan. 2009,
  • S. Mandai, T. Monma, T. Nakura, M. Ikeda, and K. Asada,
    "Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip,"
    International SoC Design Conference, Pusan, Korea, pp.89-92,Nov. 2008,
  • K. Ikai, J. Kim, M. Ikeda, and K. Asada,
    "Digital Integrated Circuit Design for System-on-Glass,"
    International SoC Design Conference, pp. 172-175, Pusan, Korea, Nov. 2008,
  • Y.K. Kim, M. Ikeda, and K. Asada,
    "Analysis on light attenuation through Multi-Metal-Layers for CMOS image sensors on System LSIs,"
    International SoC Design Conference, Pusan, Korea, No.94, Nov. 2008,
  • K. Ikai, J. Kim, M. Ikeda, and K. Asada,
    "Circuit Design using Stripe-Shaped TFTs on Glass"
    Proceedings of IEEE Asia and South Pacific Design Automation Conference, pp. 105-106, Jan. 2008,
  • S. Mandai and M. Ikeda,

    IEEE International Solid-State Circuit Conference(ISSCC), Student Forum, California, USA, SF-4-1,Feb. 2009,
  • J. Kim, K. Ikai, M. Ikeda, and K. Asada,
    " Digital Transceiver Circuit Design for Immune Device Parameter Variation,"
    IEICE Society Conference, Sep. 2008 , (in Japanese).
  • K. Ikai, J. Kim, M. Ikeda, and K. Asada,
    " Digital Integrated Circuit Design for Stripe-Shaped TFT,"
    IEICE Society Conference, Sep. 2008 , (in Japanese).
  • Y.K.Kim, M. Ikeda and K. Asada,
    " Analysis of light transmission on multilayer interconnect for color CMOS image sensors,"
    IEICE Society Conference, Sep. 2008 , (in Japanese).
  • S. Mandai, T. Nakura , M. Ikeda, K. Asada,
    " Adaptive Row-Parallel Scan 3-D Image Sensor,"
    IEICE General Conference,, Mar. 2009 , (in Japanese).
  • M. Jeong, M. Ikeda, K. Asada,
    " Dynamic Circuit Design for Selftimed Fine-grained Pipeline Architecture,"
    IEICE General Conference,, Mar. 2009 , (in Japanese).
  • D.Nakamura, H. Yoshida, S.Komatsu, M.Sasaki, M.Ikeda and K.Asada,
    " Implementation and Chip Size Evaluation of an Realtime Onchip Monitoring System for Reliability of LSI,"
    IEICE General Conference,, Mar. 2009 , (in Japanese).
  • K. Asada
    "Nanotech-Net Project as an Academic-Industry Collaboration Platform,"
    the 8th Taiwan-Japan Microelectronics Symposium 2008, 1-2, Dec.2008.
  • M. Ikeda
    "Self-Synchronous Architecture for Power Optimal Operations against PVT Variations,"
    the 8th Taiwan-Japan Microelectronics Symposium 2008, 4-6, Dec.2008.
  • M. Ikeda,
    "Smart Image Sensors,"
    University of Tokyo – INRIA – Ecole des Mines Paris – INRETS Joint Symposium on Electronics for Secure Life Jul.2008.
  • K. Asada
    "Introduction to VDEC activities for design and Manufacturing in microelectronics,"
    University of Tokyo – UC Santa Barbara Joint Workshop Sept.2008.
  • M. Ikeda
    "Delay Variation Measurements on DCVSL Using Logic Tester,"
    University of Tokyo – UC Santa Barbara Joint Workshop Sept.2008.
  • M. Ikeda
    "Self-synchronous architecture for margin aware operations against PVT variations,"
    Shanghai Jiao Tong University – University of Tokyo Joint Symposium on Electronics, Information Technology, and Electrical Engineering,D-2, Oct.2008.
  • M. Ikeda
    "Studies on Wide Dynamic Range Image Sensors,"
    IST2008-42, pp. 21-24, Information Sensing Research Committee, The Institute of Image Information and Television Engineers(ITE), Sept.2008.
  • M. Ikeda, H. Sumi
    "Report on ISSCC 2009 Medical Image Sensors Forum,"
    IST2009-11, pp. 13-16, Information Sensing Research Committee, The Institute of Image Information and Television Engineers(ITE), Mar.2009.
  • Shingo Mandai, Taihei Monma, Toru Nakura, Makoto Ikeda, and Kunihiro Asada,
    "Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip,"
    In-ternational SoC Design Conference, IEEE CAS Seoul Chapter Best Paper Award(Oral Session), Nov. 2008,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , Vol. 15, no. 6 , pp. 716--720, Jun. 2007,
  • Y.Yachide, M. Ikeda, and K. Asada,
    "Time-Division-Based Multiple-Viewpoint 3-D Measurement System for Real-Time, High-Speed, and High-Accuracy Model Movie Acquisition,"
    Journal of Image Information and Television Engineers, Vol. 62, No.3, pp. 392 -- 397, Mar. 2008,
  • Y. Yachide, M. Ikeda, and K. Asada,
    "Triangulation-based calibration method based on light-section method using spheres,"
    Proc. of International Conference on Sensing Technology (ICST), pp. 399-403,Nov. 2007,
  • Y. Yachide, M. Ikeda, and K. Asada,
    "FPGA-Based 3-D Engine for High-speed 3-D Measurement Based on Light-Section Method,"
    Proc. of IEEE International Conference on Field-Programmable Technology (ICFPT), pp. 293 - 296,Dec. 2007,
  • M. Ikeda, K. Ishii, T. Sogabe, and K. Asada,
    "Datapath Delay Distributions for Data/Instruction Against PVT Variations in 90nm CMOS,"
    Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), A4L-E04, pp. 154 - 157,Dec. 2007,
  • M. Sasaki, M. Ikeda, and K. Asada,
    "40 Frames/sec 16x16 Temperature Probe Array using 90nm 1V CMOS for On line Thermal Monitoring on VLSI Chip,"
    in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 264-267,Nov. 2007,
  • M. Sasaki, M. Ikeda, and K. Asada,
    "3.5-Gb/S Extended Frequency Range Wave-Pipeline PRBS Generator in 0.18-um CMOS,"
    Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), B2L-C04, pp. 526 - 529,Dec. 2007,
  • Hai Dinh Minh Pham, T. Iizuka, M.Ikeda, and K.Asada,
    "Shot Minimization for Throughput Improvement of Character Projection Electron Beam Direct Writing,"
    in Proc. of the SPIE (Emerging Lithographic Technologies XII), Vol. 6921, pp. 69211U-69211U-10, Feb. 2008,
  • K. Kurihara, T. Iizuka, M. Ikeda, and K. Asada,
    "Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-Meter CMOS,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), C4L-F04, pp. 1296 - 1299,Dec. 2007,
  • Y. Yachide, M. Ikeda, and K. Asada,
    "Real-time and high-speed 3-D measurement based on FPGA-based 3-D calculation,"
    Proc. of IEICE Society Conference 2007, A-3-6, p. 50,Sep. 2007, (in Japanese).
  • Hai Dinh Minh Pham, T. Iizuka, M. Ikeda, and K. Asada,
    "Shot Count Reduction Methodology for Character Projection Electron Beam Direct Writing (CP-EBDW),"
    Proc. of IEICE Society Conference 2007, A-3-12, p. 56,Sep. 2007, (in Japanese).
  • K. Ikai, M. Ikeda, and K. Asada,
    "Digital Integrated Circuit Design for Stripe-Shaped TFT,"
    Proc. of IEICE Society Conference 2007, A-3-13, p. 57,Sep. 2007, (in Japanese).
  • K. Kurihara, T. Iizuka, M. Ikeda, and K. Asada,
    "Evaluation of Cell Layout Considering Lithography Variation Tolerance,"
    Proc. of IEICE Society Conference 2007, A-3-15, p. 59,Sep. 2007, (in Japanese).
  • YunKyung Kim, M. Ikeda, and K. Asada,
    "Analysis of light's attenuation on multi-dielectric layers of a CMOS image sensor,"
    Proc. of IEICE Society Conference 2007, A-3-17, p. 61,Sep. 2007, (in Japanese).
  • Caner Basci, M. Ikeda, and K. Asada,
    "A Current-Mode Pixel-level Ambient Light Suppression Scheme for CMOS Smart Image Sensors,"
    Proc. of IEICE Society Conference 2007, C-12-7, p. 62,Sep. 2007, (in Japanese).
  • T. Nakura, T. Kazama, M. Ikeda and K. Asada,
    "Study on Active Substrate Noise Cancelling Technique using Power Line di/dt Detector,"
    CPM2007-128, ICD2007-139, pp.11-16Nov. 2007, (in Japanese).
  • T. Sogabe, M. Ikeda and K. Asada,
    "SA Self-timed Processor with Dynamic Voltage Scaling,"
    VLD2007-158, ICD2007-181, pp. 13-18Mar. 2008, (in Japanese).
  • U.H. Kim,
    "3D Modeling Method for Associative Processor,"
    Prof. IIITE, Mar. 2008, (in Japanese).
  • M. Ikeda
    "Power Control for Self-Synchronous System --Instruction and Data Grain Power Control for Self-Synchronous System with Dynamic Voltage Scaling--,"
    IEEE 2007 VAIL Computer Elements Workshop, Jun.2007.
  • M. Ikeda
    "Wide Dynamic Range on Pixel Level,"
    ISSCC2008, Imager Design Forum: Wide-Dynamic-Range Imaging, Feb.2008.
  • T. Kazama, M. Ikeda, and K. Asad,
    "LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil,"
    IEICE Trans. on Fundamentals, Vol. E89-A, No. 12, pp. 3546 -- 3550, Dec. 2006,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts,"
    in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED),, pp. 776 -- 781,Mar. 2007,
  • M. Ikeda, H. Yamauchi and K. Asada,
    "Tamper Resistivity Analysis for Nano-meter LSI with Process Variations,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 387 -- 390,Dec. 2006,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 704 -- 707,Dec. 2006,
  • Y. Yachide, M. Ikeda, and K. Asada,
    "High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 764 -- 767,Dec. 2006,
  • M. Sasaki, M. Ikeda, and K. Asada,
    "4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-um CMOS,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1007 -- 1010,Dec. 2006,
  • M. Ikeda, K.H. Dia and K. Asada,
    "Pre-conditioning Free Footless DCVSL for High-performance Datapaths,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1053 -- 1056,Dec. 2006,
  • H. Yoshida, M. Ikeda, and K. Asada,
    "Exact Minimum Logic Factoring via Quantified Boolean Satisfiability,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS),pp. 1065 -- 1068,Dec. 2006,
  • T. Kazama, T. Nakura, M. Ikeda, and K. Asada,
    "Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector,"
    in Proc. of IEEE Asian Solid-State Circuits Conference(A-SSCC), pp. 239 -- 242,Oct. 2006,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Minimum-Width Multi-Row Transistor Placement for Dual and Non-Dual CMOS Cells,"
    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5431 -- 5434,May 2006,
  • Y. Yachide, M. Ikeda, and K. Asada,
    "Realization of Real-Time High-Accuracy Multiple-Viewpoint 3-D Imaging System,"
    in Proc. of IEICE Society Conference 2006,A-1-17, p. 17,Sep. 2006, (in Japanese).
  • H. Yoshida, M. Ikeda, and K. Asada,
    "Synthesis of Read-Once Switch Network,"
    in Proc. of IEICE Society Conference 2006,A-3-9, p. 53,Sep. 2006, (in Japanese).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Minimum-Width Multi-Row Transistor Placement for Dual and Non-Dual CMOS Cells,"
    in Proc. of IEICE Society Conference 2006,A-3-20, p. 64,Sep. 2006, (in Japanese).
  • T. Kazama, T. Nakura, M. Ikeda, and K. Asada,
    "Active Substrate Noise Cancelling Method using Multiple di/dt Detectors,"
    in Proc. of IEICE Society Conference 2006,C-12-22, p. 83,Sep. 2006, (in Japanese).
  • K. Ishii, M. Ikeda, and K. Asada,
    "Evaluation of Dual-Rail Domino Logic,"
    in Proc. of IEICE Society Conference 2006,C-12-34, p. 95,Sep. 2006, (in Japanese).
  • Z. Liang, M. Ikeda, K. Asada,
    "A Monte-Carlo Analysis of Static CMOS and Dual-Rail PLA for Sub-100nm Parameter Variations,"
    in IEICE General Conference 2007,A-3-12,Mar. 2007, (in Japanese).
  • Y.S. CHO, M. Sasaki, M. Ikeda, K. Asada,

    in IEICE General Conference 2007,A-1-11,Mar. 2007, (in Japanese).
  • K. Asada
    "CMOS Image Sensors for Smart Applications,"
    the 6th Taiwan-Japan Microelectronics International Symposium, Nov.2006.
  • M. Ikeda
    "University-Industry Collaboration for Nanometer CMOS Design,"
    the 6th Taiwan-Japan Microelectronics International Symposium, Nov.2006.
  • K. Asada
    "CMOS Smart Image Sensor-3D HS Meas,"
    IEEE 2006 VAIL Computer Elements Workshop, Jun.2006.
  • K. Asada, Y. Yachide, Y. Oike, M. Ikeda
    "Real-Time High-Accuracy 3-D Imaging"
    in Proc. of International SoC Design Conference (ISOCC), Oct.2006.
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Yield-Optimized Standard Cell Layout IP Synthesis System,"
    the 8th IP Award from LSI IP Design Award CommitteesMay. 2006,(IP Award).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement,"
    in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 704 -- 707,Dec. 2006,(Best Student Paper Award).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures,"
    in Proc. of IPSJ DA Symposium 2005, pp. 121 -- 126,Aug. 2005,(IPSJ Yamashita SIG Research Award).
  • T. Nakura, M. Ikeda, and K. Asada,
    "On-Chip di/dt Detector Circuit,"
    IEICE Trans. on Electronics, Vol. E88-C, No. 5, pp. 782 -- 787, May 2005,
  • U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
    "A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells,"
    IEICE Trans. on Information and Systems, Vol. E88-D, No. 6, pp. 1159 -- 1167, Jun. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Yield Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization,"
    IEICE Trans. on Fundamentals,Vol. E88-A, No. 7, pp. 1957 -- 1963, Jul. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs,"
    IEICE Trans. on Electronics, Vol.E88-C, No.8, pp.1734-1739, Aug. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Minimum-Width Transistor Placement for Dual and Non-Dual CMOS Cells,"
    IEICE Trans. on Fundamentals,Vol. E88-A, No. 12, pp. 3485 -- 3491, Dec. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Autonomous di/dt Noise Control Scheme for Margin Aware Operation,"
    IEEE European Solid-State Circuit Conference (ESSCIRC), sess.8.G.2, pp.467-470, Sep. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Minimum-Width Transistor Placement Without Dual Constraint for CMOS Cells,"
    in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 74 -- 77,Apr. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Feedforward Active Substrate Noise Cancelling Technique using Power Supply di/dt Detector,"
    JSAP/IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech, Papers, pp. 284 -- 287,Jun. 2005,
  • Y. Yachide, Y. Oike, M. Ikeda, and K. Asada,
    "Real-Time 3-D Measurement System Based on Light-Section Method Using Smart Image Sensor,"
    in Proc. of IEEE International Conference on Image Processing(ICIP), pp. 1008 -- 1011,Sep. 2005,
  • N. Li, M. Ikeda, and K. Asada,
    "Analysis of Low Noise ThreePhase Asynchronous Data Transmission,"
    in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp. 479 -- 482,Sep. 2005,
  • M. Abbas, M. Ikeda, and K. Asada,
    "On-chip Detector for Non-Periodic High-Swing Noise Detection,"
    in Proc. of International SoC Design Conference (ISOCC), pp. 231 -- 234,Oct. 2005,
  • T.Kazama, M. Ikeda, and K. Asada,
    "Shot Reduction Technique for Character Projection Lithography using combined cell stencil,"
    in Proc. of SPIE BACUS Symposium on Photomask Technology, pp. 5992-5996,Oct. 2005,
  • K. H. Dia, R. Zheng, M. Ikeda, and K. Asada,
    "Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme,"
    in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 309 -- 312,Nov. 2005,
  • M. Ikeda, Y. Yachide, Y. Oike, and K. Asada,
    "Wavelength Identification Sensor Using MOS Photo-transistor Array Based on Metal Slit Diffraction,"
    in Proc. of International Conference on Sensing Technology (ICST), pp. 683 -- 686,Nov. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "On-chip di/dt Detector IP for Power Supply,"
    in Proc. of IP Based SoC Design Conference & Exhibition (IP-SOC), pp.160 -- 164,Dec. 2005,
  • H. Yoshida, M. Ikeda, and K. Asada,
    "An Algebraic Approach for Transistor Circuit Synthesis,"
    in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
  • M. Abbas, M. Ikeda, and K. Asada,
    "On-Chip Non-Periodic High-Swing Noise Detector,"
    in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
    in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 884 -- 889,Mar. 2006,
  • M. Abbas, M. Ikeda, and K. Asada,
    "On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function,"
    IEICE Trans. on Electron,Vol.E89-C, No.3, pp.370-376,Mar. 2006,
  • T. Yamamoto, M. Ikeda, and K. Asada,
    "Symbolic Analysis of Performance Fluctuation on Analog Circuits,"
    in Proc. of IEICE Karuizawa Workshop 2005, pp. 31 - 36,May 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures,"
    in Proc. of IPSJ DA Symposium 2005, pp. 121 - 126,Aug. 2005,
  • H. Yoshida, M. Ikeda, and K. Asada,
    "An Algebraic Approach for Synthesizing Circuits with Minimum Number of Transistors,"
    in Proc. of IPSJ DA Symposium 2005, pp. 133 - 138,Aug. 2005,
  • M. Abbas, M. Ikeda and K. Asada,
    "On-chip Detector for Non-Periodic High-Swing Noise Sensing,"
    in Proc. of International SOC Design Conference (ISOCC), pp.231-234,Oct. 2005,
  • K. Yamamoto, M.Ikeda, and K. Asada,
    "Stereo Vision with Random Pattern Light Projection,"
    ITE Technical Report, vol. 29, no. 67, pp. 13 - 16,Nov. 2005,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
    IEICE Technical Report, vol. 105, no. 442, pp. 79 - 84,Dec. 2005,
  • H. Yoshida, M. Ikeda, and K. Asada,
    "Exact Minimum Logic Factoring via Quantified Boolean Satisfiability,"
    IEICE Technical Report, vol. 105, no. 443, pp. 41 - 46,Dec. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply,"
    IEICE Trans. on Electron, Vol.E89-C, No.3, pp.364-369,Mar. 2006,
  • H. Yamauchi, M. Ikeda, K. Asada,
    "Degradation of Tamper Resistant LSI by Parameter Variation of Scaled Devices and its Countermeasures,"
    IEICE Technical Report, IT2005-79, pp.87-92,Mar. 2006,
  • T. Nakura, M. Ikeda, and K. Asada,
    "On-chip di/dt Detector IP for Power Supply,"
    IP Based SoC Design Conference & Exhibition (IP-SOC)Dec. 2005,(Best Paper Award).
  • T. Nakura, M. Ikeda, and K. Asada,
    "On-Chip di/dt Detector Circuit,"
    IEICE Trans. on Electronics,Vol. E88-C, No. 5, pp. 782 -- 787, May. 2005,(IEICE Best Paper Award 2005).
  • T. Nakura, M. Ikeda, and K. Asada,
    "di/dt Detector Core for Power Supply of LSI,"
    7th IP Award from LSI IP Design Award CommitteesMay. 2005,(the Outstanding IP Award 2005).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Yield-Optimized CMOS Logic Cell Layout IP Synthesis System,"
    7th IP Award from LSI IP Design Award CommitteesMay. 2005,(Development Promotion).
  • Y. Oike, M. Ikeda, and K. Asada,
    "Design and Implementation of Real-Time 3-D Image Sensor With 640 x 480 Pixel Resolution,"
    IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, pp. 622 -- 628, Apr. 2004,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits,"
    IEICE Trans. on Electronics,Vol. E87-C, No. 6, pp. 1069 -- 1077, Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Smart Image Sensor with High-Speed and High-Sensitivity ID Beacon Detection for Augmented Reality System,"
    Journal of Image Information and Television Engineers, Vol. 58, No. 6, pp. 835 -- 841, Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement Based on Light-Section Method,"
    Int. Journal of Intelligent Automation and Soft Computing (AutoSoft), AutoSoft Press, Vol. 10, No. 2, pp. 105 -- 128, Jun. 2004,
  • K. Asada, and Y. Oike,
    "Real-Time and High-Resolution 3-D Imaging System Based on Light-Section Method,"
    Image Lab, Japan Industrial Publishing Co., Vol. 15, No. 7, pp. 40 -- 44, Jul. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A High-Speed and Low-Voltage Associative Co-Processor With Exact Hamming/Manhattan-Distance Estimation Using Word-Parallel and Hierarchical Search Architecture,"
    IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, pp. 1383 -- 1387, Aug. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories,"
    IEICE Trans. on Electronics, Vol. E87-C, No. 11, pp. 1847 -- 1855, Nov. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "High-Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability,"
    IEICE Trans. on Fundamentals, Vol. E87-A, No. 12, pp. 3293 -- 3300, Dec. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition,"
    IEICE Trans. on Electronics, Vol. E87-C, No. 12, pp. 1651 -- 1658, Dec. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability,"
    IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3293-3300,Dec. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A 375 x 365 High-Speed 3-D Range-Finding Image Sensor Using Row-Parallel Search Architecture and Multi-Sampling Technique,"
    IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 444 -- 453, Feb. 2005,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Stub vs. Capacitor for Power Supply Noise Reduction,"
    IEICE Trans. on Electronics , Vol.E88-C, No.1, pp.125-132, Jan. 2005.
  • U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
    "Constraint Driven Dual-Rail PLA Module Generator with Embedded 2-Input Logic Cells,"
    in Proc. of IEEE Mediterranean Electrotechnical Conference (MELECON), pp. 189 -- 192,May 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A Pixel-Level Color Image Sensor With Efficient Ambient Light Suppression Using Modulated RGB Flashlight and Application to TOF Range Finding,"
    IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech., Papers, pp. 298 -- 301,Jun. 2004,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Power Supply di/dt Measurement using On-chip di/dt Detector Circuit,"
    IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech., Papers, pp. 106 -- 109,Jun. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A High-Speed XGA 3-D Image Sensor and Its Applications,"
    in Proc. of the 6th Biannual World Automation Congress (WAC 2004),Jun. 2004,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Design and Measurement of On-chip di/dt Detector Circuit for Power Supply Line,"
    in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), University Design Forum, pp. 426 -- 427,Aug. 2004,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Preliminary Experiments for Power Supply Noise Reduction using Stubs,"
    in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), pp. 286 -- 289,Aug. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Design and Implementation of Word-Parallel Digital Associative Memories,"
    in Proc. of IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), University Design Forum, pp. 428 -- 429,Aug. 2004,
  • U. Ekinciel, M. Ikeda, and K. Asada,
    "An SRAM-based Field Programmable Logic Array Design,"
    IEICE Society Conference 2004,Sep. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A Word-Parallel Digital Associative Engine with Wide Search Range Based on Manhattan Distance,"
    in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 295 -- 298,Oct. 2004,
  • M. Abbas, M. Ikeda, and K. Asada,
    "Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime,"
    in Proc. of The 19th IEEE International Symposium on Deffet and Fault Tolerance in VLSI Systems (DFT 2004), pp, 87 -- 97,Oct. 2004,
  • M. Abbas, M. Ikeda, and K. Asada,
    "On High Noise Immunity CMOS Design Scheme with Low Leakage Power Consumption,"
    in Proc. of The 17th International Conference on Solid State and Integrated-Circuit Technology (ICSICT 2004), pp, 2031 -- 2034,Oct. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture,"
    in Proc. of IP Based System-on-Chip Design Forum & Exhibition (IP-SOC), pp. 127 -- 130,Dec. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A High-Speed 3-D Range Finder Using Row-Parallel Search Architecture,"
    IEICE Technical Report, vol. 104, no. 174, pp. 7 - 10,Jun. 2004, (in Japanese).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Minimum-Width Transistor Placement Method via Boolean Constraints for Non-Complementary Transistors,"
    in Proc. of IPSJ DA Symposium 2004, pp. 121 - 126,Jul. 2004, (in Japanese).
  • Y. Oike, M. Ikeda, K. Asada,
    "A 1024 x 768 High-Speed and High-Accuracy 3-D Image Sensor,"
    in Proc. of ITE Annual Conference 2004, 19-1,Aug. 2004, (in Japanese).
  • T. Nakura, M. Ikeda, K. Asada,
    "Power Supply Noise Reduction on LSIs using Off-chip stubs,"
    in Proc. of IEICE Society Conference 2004, C-12-1,Sep. 2004, (in Japanese).
  • Y. Oike, M. Ikeda, K. Asada,
    "Design of Digital Associative Engine for Manhattan Distance Search,"
    in Proc. of IEICE Society Conference 2004, C-12-7,Sep. 2004, (in Japanese)
  • M. Abbas, M. Ikeda, K. Asada,
    "Statistical Evaluation of Logic Errors in Low Power Design Schemes,"
    in Proc. of IEICE Society Conference 2004, A-9-3,Sep. 2004, (in Japanese)
  • N. Li, M. Ikeda, K. Asada,
    "Study of Low EMI Circuit with 3-Phase Transmission Protocol,"
    in Proc. of IEICE Society Conference 2004, C-12-5,Sep. 2004, (in Japanese)
  • TH. YEN, M. Ikeda, K. Asada,
    "Estimatoin of Radiated Electromagnetic Emission from Integrated Circuit Using Short Wire Antenna,"
    in Proc. of IEICE Society Conference 2004, B-4-30,Sep. 2004, (in Japanese)
  • Y. Oike, H. Hashimoto, M. Ikeda, K. Asada,
    "A Color Demodulation Image Sensor for Support of Image Recognition,"
    ITE Technical Report, Vol. 28, No. 59, pp. 9 -- 12,Oct. 2004, (in Japanese)
  • Y. Yachide, Y. Oike, M. Ikeda, K. Asada,
    "Implementation of a Real-Time 3-D Imaging System and Application to Multi-Viewpoint Measurement,"
    in Proc. of IEICE the 8th Workshop on System LSI in Kitakyushu, pp.255-258,Nov. 2004, (in Japanese)
  • T. Iizuka, H. Yoshida, M. Ikeda, K. Asada,
    "Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability,"
    IEICE Technical Report, vol. 104, no. 478, pp. 1 - 6,Dec. 2004, (in Japanese)
  • H. Yoshida, K. De, V. Boppana, M. Ikeda, K. Asada,
    "Accurate Pre-Layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement,"
    IEICE Technical Report, vol. 104, no. 478, pp. 7 - 12,Dec. 2004, (in Japanese)
  • Y. Oike, M. ikeda, and K. Asada,
    "A High-Speed Associative Processor Using Hierarchical Search Architecture Based on Hamming Distance,"
    6th IP Award from LSI IP Design Award CommitteesJun. 2004,(the Outstanding IP Award 2004).
  • K. Seto, M. Fujita, and K. Asada,
    "Optimal Code Generation Based on Boolean Satisfiability,"
    IPSJ Journal, Vol. 43, No. 5, May 2003,
  • Y. Oike, H. Shintaku, M. Ikeda, and K. Asada,
    "A High-Resolution and Real-Time 3-D Imaging System Based on Light-Section Method,"
    Journal of Image Information and Television Engineers, Vol. 57, No. 9, pp. 1149 - 1151, Sep. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High Performance Photo Detector for Correlative Feeble Lighting Using Pixel-Parallel Sensing,"
    IEEE Sensors Journal, vol. 3, no. 5, pp. 640 - 645, Oct. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method,"
    IEICE Trans. on Electronics, Vol. E86-C, No. 11, pp. 2320 - 2328, Nov. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A 120 x 110 Position Sensor With the Capability of Sensitive and Selective Light Detection in Wide Dynamic Range for Robust Range Finding,"
    IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp. 246 - 251, Jan. 2004,
  • H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
    "A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture,"
    IEICE Trans. Electron., vol. E87-C, no. 2, pp. 238-245, Feb. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-Speed Position Detector Using New Row-Parallel Architecture For Fast Collision Prevention System,"
    in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 4, pp.788 - 791,May 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "640x480 Real-Time Range Finder Using High-Speed Readout Scheme and Column-Parallel Position Detector,"
    IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech, Papers, pp.153 - 156,Jun. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A Smart Image Sensor With High-Speed Feeble ID-Beacon Detection for Augmented Reality System,"
    in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp.125 - 128,Sep. 2003,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed Logic Circuit Family with Interdigitated Array Structure for Deep Sub-Micron IC Design,"
    Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 189-192, Portugal,Sep. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A High-Speed and Low-Voltage Associative Co-Processor With Hamming Distance Ordering Using Word-Parallel and Hierarchical Search Architecture,"
    in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp.643 - 646,Sep. 2003,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Theoretical Study of Stubs for Power Line Noise Reduction,"
    in Proc. of IEEE Custom Integrated Circuits Conference (CICC), 31-4, pp.715-718, Sep. 2003,
  • Y. Oike, H. Shintaku, S. Takayama, M. Ikeda, and K. Asada,
    "Real-Time and High-Resolution 3-D Imaging System Using Light-Section Method and Smart CMOS Sensor,"
    in Proc. of IEEE International Conference on Sensors (IEEE SENSORS), pp. 502 - 507,Oct. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Design of Real-Time VGA 3-D Image Sensor Using Mixed-Signal Techniques,"
    in Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 523 - 524,Jan. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability,"
    in Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149 - 154,Jan. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "HA 375 x 365 3D 1k frame/s Range-Finding Image Sensor with 394.5 kHz Access Rate and 0.2 Sub-Pixel Accuracy,"
    IEEE International Solid-State Circuits Conference (ISSCC) Dig. of Tech, Papers, pp. 118 - 119,Feb. 2004,
  • T. Nakura, M. Ikeda, and K. Asada,
    "On-chip di/dt Detector Circuit for Power Supply Line,"
    in Proc. of IEEE International Conference on Microelectronic Test Structure (ICMTS), pp.19-22,Mar. 2004,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells,"
    in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 377 - 380,Mar. 2004,
  • K. Asada, Y. Oike, and M. Ikeda,
    "Three Dimensional Image Sensor for Real Time Application Based on Triangulation,"
    in Proc. of International Symposium on Electronics for Future Generations, pp. 95 - 100,Mar. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Smart Active Range Finder With the Capability of High Sensitivity, High Selectivity and Wide Dynamic Range,"
    IEICE Technical Report, vol. 103, no. 89, pp.7-12,May 2003,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Cell Layout Synthesis via Boolean Satisfiability,"
    in Proc. of IPSJ DA Symposium 2003, pp. 139 - 144,Jul. 2003,
  • Y. Oike, H. Shintaku, M. Ikeda and K. Asada,
    "A Real-Time and High-Resolution 3-D Imaging System Using Smart CMOS Image Sensor,"
    in Proc. of ITE Annual Conference 2003, 20-9, pp. 299-300,Aug. 2003,
  • Y. Oike, M. Ikeda and K. Asada,
    "A High-Speed and Low-Voltage Associative Co-Processor With Hamming Distance Ordering Using Word-Parallel and Hierarchical Search Architecture,"
    in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp.643-646,Sep. 2003,
  • Y. Oike, M. Ikeda and K. Asada,
    "High-Performance Photo Detector for Correlative Feeble Lighting Using Pixel-Parallel Sensing,"
    IEEE Sensors Journal 2002 Sensors Conf. Florida, Vol.3, No.5, pp.640-645,Oct. 2003,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells,"
    IEICE Technical Report, vol. 103, no. 476, pp. 157 - 161,Nov. 2003,
  • T. Nakura, M. Ikeda, and K. Asada,
    "Power Supply Noise Reduction using Stubs,"
    IEICE Technical Report, vol. 103, no. 476, pp. 217 - 222,Nov. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "An Image Sensor with High-Speed Feeble ID Beacon Detection for Augmented Reality System,"
    in Proc. of ITE Winter Conference 2003, 4-1, pp. 34,Dec. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A 375x365 3D 1k frame/s Range-Finding Image Sensor with 394.5kHz Access Rate and 0.2 Sub-Pixel Accuracy,"
    IEEE International Solid-State Circuits Conference (ISSCC) Deg. of Tech. Papers, pp.118-119,Feb. 2004.
  • T. Nakura, M. Ikeda, and K. Asada,
    "Recent Trend of Circuit Designs,"
    JIEP Technical Report, pp.131-132,Mar. 2004,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A High-Speed and Low-Voltage Associative Co-Processor Using Word-Parallel and Hierarchical Search Architecture,"
    in Proc. of IEICE General Conferece 2004, C-12-34, pp. 138,Mar. 2004,
  • H. Ikehata, M. Song, M. Ikeda, and K. Asada,
    "Comparison between DCVSL Domino and Static CMOS by High Speed MULTIPLIER,"
    in Proc. of IEICE General Conferece 2004, A-1-13, pp. 13,Mar. 2004,
  • T. Ogawa, M. Ikeda, and K. Asada,
    "Analysis on Contactless Data Transfer Systems between System LSIs,"
    in Proc. of IEICE General Conferece 2004, A-1-22, pp. 22,Mar. 2004,
  • Y. Yachide, Y. Oike, M. Ikeda, and K. Asada,
    "3D Measurement Method in an Arbitrary Viewpoint Based on Light-Section Method by Using Smart Image Sensor,"
    ITE Technical Report, Vol. 28, No. 20, pp. 33 - 36,Mar. 2004,
  • Y. Oike, M. ikeda, and K. Asada,
    "High-Sensitivity and Wide-Dynamic-Range Range Finder With Ambient Light Suppression,"
    5th IP Award from LSI IP Design Award CommitteesJun. 2003,(IP Award 2003).
  • H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada,
    "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells,"
    5th IP Award from LSI IP Design Award CommiteesJun. 2003,(IP Award 2003).
  • Y. Oike, M. ikeda, and K. Asada,
    "Design of Real-Time VGA 3-D Image Sensor Using Mixed-Signal Techniques,"
    IEEE Asia and South Pacific Design Automation Conference (ASP-DAC)Jan.. 2004,(the Best Design Award).
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit,"
    IEICE Trans. on Electronics, Vol. E85-C, No. 8, pp.1651 - 1658, Aug. 2002,
  • K. Asada, T. Nezuka, and Y. Oike,
    "Smart Access Sensors,"
    Optronics, vol. 20, no. 237, pp. 136 - 141, Sep. 2002,
  • Y.Murakami and K. Asada,
    "GTBT:Grounded-Trench-MOS Assisted Bipolar-Mode FET,"
    IEICE Trans. on Electron., Vol. J85-C, No. 9, pp. 828 - 837, Sep. 2002,
  • M. Song, K. Asada,
    "Design of a Conditional Sign Decision Booth Encorder for a High Performance 32 x 32-Bit Digital Multiplier,"
    IEICE Trans. on Electron., Vol. E85-C, No. 9, pp. 1709 - 1717, Sep. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "A CMOS Image Sensor for High-Speed Active Range Finding Using Column-Parallel Time-Domain ADC and Position Encoder,"
    IEEE Trans. on Electron Devices, Vol. 50, No. 1, pp.152 - 158, Jan. 2003,
  • M. Ikeda, et al
    "Frequency-dependent electrical characteristic of DNA using molecular dynamics simulation,"
    Nanotechnology, Vol. 14, pp.123 - 127, Jan. 2003,
  • K. Asada,
    "VLSI Design Activities in Japanese Academia and Future Prospects toward SoC Design in Deep-sub micron technologies,"
    The 2nd Taiwan-Japan Microelectronics International Symoposium, pp.235-242, Apr. 2002,
  • H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
    "Logic Synthesis for PLA with 2-input Logic Elements,"
    in Proc. of IEEE Int. Symp. on Circuits and System, pp.373-376, May 2002,
  • T. Ishihara, S. Komatsu,M. Miyama,M. Yoshimoto, M. Hirata, M. Fujita and K. Asada,
    "An Inter-University Joint Program for a Trial of IP-Based System LSI Design,"
    Proc. of the 4th European Workshop on Microelectronics Education, pp.129-132, May 2002,,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High Performance Photo Detector for Modulated Lighting,"
    in Proc. of IEEE International Conference on Sensors (IEEE SENSORS), pp.1456 - 1461, Jun. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-sensitivity and Wide-dynamic-range Range Finder and Its Applications,"
    in Proc. of the 5th Biannual World Automation Congress (WAC 2002), pp.417 - 422, Jun. 2002,
  • T. Iizuka, and K. Asada,
    "An Exact Algorithm for Practical Routing Problems,"
    in Proc. of the Third IEEE Asia-Pacific Conference on ASICs (AP-ASIC), pp.343 - 346, Aug. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-sensitivity and Wide-dynamic-range Position Sensor Using Logarithmic-response and Correlation Circuit,"
    IEICE Transactions on Electronics,Vol.E85-C, No.8, pp.1651-1658, Aug. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Smart Sensor Architecture for Real-Time and High-Resolution Range Finding,"
    in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp.105 - 108, Sep. 2002,
  • M. Ikeda, et al.
    "Frequency-dependent electrical characteristic of DNA using molecular dynamics simulation,"
    Trends on Nanotechnology, Sep. 2002,
  • M. Ikeda, et al.
    "Quick Calculation Method of LSI Power Supply Noise,"
    9th IEEE Int. Conf. on Electron., Circuits and Systems, Sep. 2002,
  • H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
    "A Dual-Rail PLA with 2-Input Logic Cells,"
    Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 203-206, ,Sep. 2002,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed Functional Memory with a Capability of Hamming-Distance-Based Data Search by Dynamic Threshold Logic Circuits,"
    Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 667-670, ,Sep. 2002,
  • U. Ekinciel, H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada,
    "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells,"
    IEICE Society Conference 2002, Sep. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "An Active Range Finder With the Capability of -18 dB SBR, 48 dB Dynamic Range and 120 x 110 Pixel Resolution,"
    IEEE International Solid-State Circuits Conference (ISSCC) Dig. of Tech. Papers, pp.208 - 209, Feb. 2003,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A Smart Position Sensor with Row Parallel Position Detection for High Speed 3-D Measurement,"
    in Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp.101 - 105, Sep. 2002,
  • Ulkuhan Ekinciel, H. Yamaoka, and K. Asada,
    "A Module Generator for Dual-Rail PLA with 2-Input Logic Cells,"
    IEICE Society Conf.,A-3-7, pp.62, Sep. 2002,
  • Yoshinori Murakami and K. Asada,
    "GTBT:Development of a Grounded-Trench MOS-Assisted Bipolar-Mode FET,"
    Electronics and Communications in Japan, Part2, Vol.87, No.3, pp.828-837, Sep. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-Speed Content-Addressable Memory Using Synchronous Hamming Distance Search Circuits,"
    IEICE Technical Report, vol. 102, no. 2, pp.19-24, Apr. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Smart Sensor Architecture for Real-Time High-Resolution 3-D Measurement and Its Implementation,"
    ITE Technical Report, vol. 26, no. 41, pp.37-40, Jun. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High Perfomance Photo Detector for Modulated Lighting,"
    in Proc. of IEEE International Conference on Sensors (IEEE SENSORS), pp.1456-1461, Jun. 2002,
  • T. Ishihara, and K. Asada,
    "A Threshold Voltage Scheduling Technique for High Performance and Low Leakage On-chip Memory,"
    IPSJ DA Symposium, pp.55 - 60, Jul. 2002,
  • S. Sugiyama, M. Ikeda, and K. Asada,
    "Quick Calculation Method of LSI Power Supply Noise,"
    SCAE2002-6, pp.19 - 24, Jul. 2002,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A Dual-Rail PLA with 2-Input Logic Cells,"
    IEICE Technical Report, SDM2002-156, Future University-Hakodate, Aug. 2002,
  • T. Yamamoto, and K. Asada,
    "A Method for Reducing Inductive Coupling Noise by Using 3-Phase Data Encoding,"
    IEICE Tech. Report, pp.25 - 30, Aug. 2002,
  • S.Sugiyama, M.Ikeda and K. Asada,
    "Quick Power Supply Noise Estimation Using Hierarchically Derived Transfer Functions,"
    9th IEEE Int. Conf. on Electron., Circuits and Systems (ICECS2002), Sep. 2002,
  • T. Iizuka, M. Ikeda, and K. Asada,
    "An Exact Algorithm for Practical Routing Problems,"
    in Proc. of IEICE Society Conference 2002, A-3-6, pp. 61, Sep. 2002,
  • Shen XB., T. Nakura, M. Ikeda, and K. Asada,
    "The Estimation of Reliability Using Error Propagation,"
    in Proc. of IEICE Society Conference 2002, C-12-6, pp. 72, Sep. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-Speed Position Detector Using Row-Parallel Architecture for Fast Collision Prevention System,"
    IEICE Technical Report, vol. 102, no. 399, pp.7-11, Oct. 2002,
  • Y. Oike, T. Nezuka, M. Ikeda, and K. Asada,
    "Challenges to Real-Time 3-D Imaging Based on Light-Section Method,"
    JTTAS The 85th Regular Meeting of Next-Generation Vision System Committee, Nov. 2002,
  • K. Asada, Y. Oike, M. Ikeda,
    "Intelligent Imaging and Pre-Processing: Real-Time/Robust 3-D CMOS Imager,"
    in Proc. of Scientific Research on Priority Areas Symposium,pp.3-15,Mar. 2003,
  • H. Shintaku, Y. Oike, S. Takayama, M. Ikeda, and K. Asada,
    "Design of FPGA for Real-Time 3-D Imager Control and Fast Data Transmission,"
    in Proc. of IEICE General Conference 2002, D-11-67, pp.67,Mar. 2003,
  • Y. Oike, M. Ikeda, and K. Asada,
    "640x480 Real-Time Range Finder Based on Light-Section Method,"
    ITE Technical Report, vol. 27, no. 25, pp.1-4,Mar. 2003,
  • S. Sugiyama, M. Ikeda and K. Asada,
    "Quick Noise Estimation Using Multi Terminal F-matrix in Power Grid Model,"
    IEICE Tech. Report, Vol. 102, No. 683, VLD 2003-150, pp. 25-30,Mar. 2003,
  • T. Yamamoto, M. Ikeda and K. Asada,
    "Inductance Calculation for Rectangle Section Form Wiring using GMD,"
    IIEICE Gen. Conf., A-3-16, pp. 83,Mar. 2003,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed Functional Memory with a Capability of Hamming-Distance-Selective Data Search Using Threshold Logic Circuits,"
    IEICE Technical Report, VLD2002-151, pp. 31-36, Campus Plaza Kyoto,Mar. 2003,
  • U. Ekinciel, H. Yamaoka, M. Ikeda, and K. Asada,
    "Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells,"
    IEICE Technical Report,VLD2003, Mar. 2003,
  • K. Asada,
    "Fundamentals and Advanced Features for VLSI Design Activities Supported by Kunihiro Asada, VDEC, Japan,"
    1CFES 2002 (The International Conference on Fundamentals of Electronics, Communications and Computer Sciences) Mar.27-28, 2002, Waseda Univ.,
  • K. Asada,
    "AFuture opening Semiconductor Technology - Number of VLSI design researchers in Universities becomes 4 times in 6 years, IP reuse enbiromentation,"
    Nikkei Micro Device, Special Ed., pp.7, Mar. 2002,
  • K. Asada,
    "VLSI Design Activities in Japanese Academia and Future Prospects toward SoC Design in Deep-sub micron technologies,"
    The 2nd Taiwan-Papan Microelectronics International Symoposium, pp.235-242 (National Chiao Tung University, Hsinchu, Taiwan 新竹 国立交通大学), Apr. 2002,
  • Y. Oike, M. ikeda, and K. Asada,
    "High-Speed Content-Addressable Memory Using Synchronous Hamming Distance Search Circuit,"
    4th IP Award from LSI IP Design Award CommitteesMay. 2002,(IP Award 2002).
  • H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada,
    "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells,"
    4th IP Award from LSI IP Design Award CommiteesJun. 2003,(IP Award 2002).
  • T. Iizuka, M. Ikeda, and K. Asada,
    "An Exact Algorithm for Practical Routing Problems,"
    in Proc. of IEICE Society Conference 2002, A-3-6, pp. 61, Sep. 2002,(IEICE Young Researcher's Award).
  • H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
    "Logic Synthesis for AND-XOR-OR type Sense-Amplifying PLA,"
    Proceedings of the 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (India) IEEE Int. Conf. on VLSI Design & ASP-DAC, pp. 166-171, Jan. 2002,
  • T. Ishihara and K. Asada,
    "An Architectural Level Energy Reduction Technique for Deep-Submicron Cache Memories,"
    ASP-DAC 2002 (India), pp.274-287, Jan. 2002,
  • K. Asada, T. Nezuka, and Y. Oike,
    "Real-Time 3-D Measurement System Using Smart Access Image Sensor,"
    in Proc. of Scientific Research on Priority Areas Symposium, pp.3-12, Mar. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "New Pixel Architecture for High-Sensitivity Position Detection,"
    in Proc. of IEICE General Conference 2002, C-12-47 集積回路C(アナログ) pp.129, Mar. 2002,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-sensitivity and Wide-dynamic-range Position Sensor Using Logarithmic-response and Correlation Circuit,"
    IEEE Int. Conf. on VLSI Design & ASP-DAC (the Best Design Award)", Jan. 2002,
  • K. Asada,
    "Future opening Semiconductor Technology-Number of VLSI design reserchers in Universities becomes 4 times in 6 yers, IP reuse enbiromentation,"
    未来を切り拓く半導体技術 日経マイクロデバイス特別編集版 Nikkei Micro Device, Special Ed., pp。7, Mar. 2002,
  • K. Asada,
    "Fundamentals and Advanced Features for VLSI Design Activities Supported by Kunihiro Asada, VDEC, Japan,"
    ICFES 2002 (The International Conference on Fundamentals of Electronics, Communications and Computer Sciences) Mar.27-28, 2002, Waseda Univ., SS-4 Roles ofChip Fabrication Service for VLSI Design Educaation, Mar. 2002,
  • K. Asada,
    (in Japanese) "日本半導体産業の復権 2010年までの半導体技術展望 「LSI設計力の高度化」,"
    電波新聞 (電波新聞社 Tel3445-8715), 2001.1.17, Jan. 2001,
  • T. Yamashita and K. Asada,
    "Offset-Cancelling Sense Amplifier Applied with Pass-Transistor Logic ,"
    電子情報通信学会論文誌 C , Vol.J84-C, No.2, pp.144-150, Feb. 2001,
  • T. Ishihara and K. Asada,
    "A System Level Memory Power Optimization Technique Using Multiple Supply and Threshold Voltages,"
    Proc. Asia and South Pacific Design Automation Conference 2001 (ASP-DAC), Yokohama, pp.456-461, Jan. 2001,
  • Y. Nakashima, M. Ikeda, and K. Asada,
    "Computational Cost Reduction in Extracting Inductance,"
    International Symposium on Quality Electronic Design (ISQED), Mar. 2001,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed PLA using Array Logic Circuits with Latch Sense Amplifiers and a Charge Sharing Scheme,"
    Proc. Asia and South Pacific Design Automation Conference 2001 (ASP-DAC), Yokohama, pp.3-4, Jan. 2001,
  • K. Asada, T. Nezuka, Y. Oike, and M. Hoshino,
    (in Japanese) "3次元計測向けスマートセンサ,"
    平成12年度 特定領域研究シンポジウム「知的瞬時処理複合化数隻システム」, pp.3-8, Mar. 2001,
  • Y. Oike, M. Ikeda, and K. Asada,
    "An Image Sensor for 3-D Measurement with Correlation Technique,"
    2001年電子情報通信学会総合大会, C-12-27, Mar. 2001,
  • T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
    "A Smart Position Sensor for 3-D Measurement,"
    Proceedings of ASP-DAC 2001, pp.21-22, Feb. 2001,
  • T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
    "A Smart Image Sensor with Quad-tree Scan,"
    Journal of Image Information and Television Engineers, Vol.55, No.2, pp.287-292, Feb. 2001,
  • J. Qiao, M.Ikeda, and K.Asada,
    "Finding an Optimal Functional Decomposition for LUT-based FPGA Syntesis,"
    Asia and South Pacific Design Automation Conference 2001(ASP-DAC), Yokohama, pp.225-230, Feb. 2001,
  • K. Hoh, K. Asada, and M. Ikeda,
    (in Japanese) "大規模集積システム設計教育研究センターによるVLSI設計教育・研究の支援,"
    電気学会論文誌C(電子・情報・システム部門誌) Trans. IEE of Japan, Vol.121-C, No.3, pp.488-491, Mar. 2001,
  • S. Sugiyama, M. Ikeda, K. Asada, and H. Aoki,
    "Evaluation Using Transfer Function and Analysis of Power Supply Noise,"
    電子情報通信学会 VLD研究会, Mar. 2001,
  • T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
    "A Binary Image Sensor for Motion Detection,"
    Journal of Robotics and Mechatronics, Vol.12 No.5, pp.508-514, Jun. 2001,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A Smart Position Sensor for 3-D Measurement,"
    Proceedings of JSME Conference on Robotics and Mechatronics   日本機械学会ロボティクス・メカトロニクス講演会 , 2P1-N1, May. 2001,
  • T. Ishihara and K. Asada,
    "A System Level Optimization Technique for Application Specific Low Power Memories ,"
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E84-A, No.11, pp.2755-2761, Nov. 2001,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed PLA using Dynamic Array Logic Circuits with Latch Sense,"
    IEICE Transactions on Electronics, Vol.E84-C, No.9, pp.1240-1246, Sep. 2001,
  • H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
    "Logic Synthesis for XOR-Based Dual-Rail PLA,"
    DAシンポジウム 情報処理学会 in Proc. of IPSJ DA Synposium, pp.31-36, Jul. 2001,
  • J. Qiao and K. Asada,
    "Functional Decomposition with Application to LUT-Based FPGA Synthesis,"
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E84-A No.8 p.2004-2013, Aug. 2001,
  • K. Asada,
    "Current status of VDEC IP project and future plan,"
    電子情報通信学会技術研究報告 VLSI設計技術, VLSI2001-85-88, pp.1-13, Nov. 2001,
  • H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
    "Logic Synthesis for PLA with 2-input Logic Elements,"
    電子情報通信学会技術報告, CPSY2001-72, Nov. 2001,
  • H. Yamaoka and K. Asada,
    "A Threshold Logic-Based High-Speed Hamming Distance Detector and Its Evaluation,"
    電子情報通信学会技術研究報告 ICD, SDM2001-134, pp. 37-42, Aug. 2001,
  • K. Asada, T. Nezuka, and Y. Oike,
    "Smart Access Sensor,"
    オプトロニクス, 9月号, pp.136-141, Sep. 2001,
  • T. Ishihara and K. Asada,
    "A Leak Energy Reduction Techineque for Deep Submicron Cache Memories,"
    信学技報 IEICE Technical Report, CPSY2001-61,pp.1-6, Nov. 2001,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Design and Evaluation of High-sensitivity and Wide-dynamic-range Position Sensor for 3-D Measurement,"
    第5回 システムLSIワークショップ, pp.307-310, Nov. 2001,
  • Y. Oike, M. Ikeda, and K. Asada,
    "High-speed and High-accuracy Position Sensor for 3-D Measurement Using Row Parallel Processing on the Sensor Plane,"
    電子情報通信学会技術研究報告, ICD2001-103, pp.83-88, Sep. 2001,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Design of Wide Dynamic Range Photo Detector Using Log-response and Correlation Circuit,"
    DAシンポジウム2001 Prc. Of IPSJ DA Symposium, pp.159-161, Jul. 2001,
  • Y. Oike, M. Ikeda, and K. Asada,
    "Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-response and Correlation Circuit,"
    Ext. Abst. of Int. Conf. of Solid State Devices and Materials, pp.282-283, Sep. 2001,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A High-Speed Position Sensor for 3-D Measurement with Column Parallel Readout,"
    第5回システムLSIワークショップ, pp.231-234, Nov. 2001,
  • S. Sugiyama, M. Ikeda, and K. Asada,
    "Power Supply Noise Estimation Using Transfer Function,"
    IEICE Technical Report, VLD2001-157, Nov. 2001,
  • H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada,
    "Logic Synthesis for PLA with 2-input Logic Elements,"
    電子情報通信学会技術研究報告、北九州国際会議場, CPSY2001-72,pp.67-72, Nov. 2001,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "An Implementation Method of High-Speed Row Parallel Position Detection on Sensor Plane,"
    電子情報通信学会技術研究報告, ICD2001-101, pp.67-74, Sep. 2001,
  • K. Asada, M. Ikeda, and S. Komatsu,
    "Approaches for Reducing Power Consumption in VLSI Bus Circuits,"
    IEICE Trans. Electronics, Vol.E83-C, No.2, pp.153-160, Feb. 2000,
  • T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
    "A Binary Image Sensor with Flexible Motion Vector Detection using Block Matching Method,"
    Proceedings of ASP-DAC 2000, University LSI Design Contest, A1.11, pp.21-22, Feb. 2000,
  • Y. Nakashima, M. Ikeda, and K. Asada,
    "Computational Cost Reduction in Extracting VLSI Interconnect,"
    2000年電子情報通信学会総合大会, A-3-15, Mar. 2000,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Circuit Evaluation of Adaptive Code-Book Encoding for Low Power Chip-Interface,"
    2000年電子情報通信学会総合大会, C-12-14, Mar. 2000,
  • T. Yamashita and K. Asada,
    "CSPL: A Capacitor-Separated Pass-transistor Logic using Self Offset-Cancelling Sense Amplifier for high speed operation,"
    2000年電子情報通信学会総合大会, C-12-17, Mar. 2000,
  • M. Hoshino and K. Asada,
    "A 3-D Measurement System using Smart Image Sensor with Flexible Block Access,"
    2000年電子情報通信学会総合大会, C-12-51, Mar. 2000,
  • H. Aoki, M. Ikeda, and K. Asada,
    "On-Chip Voltage Noise Monitor for Measuring Voltage Bounce in Power Supply Lines Using a Digital Tester,"
    International Conference on Microelectronic Test Structures 2000 (ICMTS2000)  , Session4.9, Mar. 2000,
  • M. Ikeda, H. Aoki, and K. Asada,
    "DVDT: Design for Voltage Drop Test using Onchip-Voltage Scan Path,"
    2000 IEEE International Symposium on Quality Electronic Design(ISQED2000),, Mar. 2000 (To be presented), Mar. 2000,
  • M. Ikeda, H. Aoki, and K. Asada,
    "Noise Measurement on Power Supply Lines using OnChip Voltage Scan Path,"
    14th JIEP General Conference (第14回 エレクトロニクス実装学会 学術講演大会), Mar. 2000,
  • Y. Nakashima, M. Ikeda, and K. Asada,
    "New method for calculating inductance on VLSI circuit,"
    電子情報通信学会総合大会, pp.83, A-3-15, Mar. 2000,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed PLA with Latch Sense Amplifiers,"
    電子情報通信学会総合大会, C-12-16, p. 111, Mar. 2000,
  • T. Mido, H. Ito, and K. Asada,
    "A Simple and Efficient Measurement Method for Characterizing Capacitance Matrix of Multilayer Interconnection in VLSI,"
    IEEE Transacions on Semiconductor Manufacturing, Vol.13, No.2, pp.145-151, May. 2000,
  • K. Hoh and K. Asada,
    (in Japanese) "大規模集積システム設計教育研究センター(VDEC)による集積回路の設計教育と試作の支援,"
    平成12年度工学教育連合講演会「21世紀における日本の工学教育ー"ものづくり"と"創造性"」, 2000/05/10, May. 2000,
  • T. Ishihara and K. Asada,
    "A Memory Power Reduction Technique for Core-base System LSIs,"
    電子情報通信学会 技術研究報告 VLD2000-85, VLD200-85, pp.95-100, 2000,
  • T. Yamashita and K. Asada,
    "CSPL: A Capacitor-Separated Pass-Transistor Logic for High Speed and Low Voltage Operation,"
    電子情報通信学会論文誌 C , Vol.J83-C, No.6, pp.479-486, Jun. 2000,
  • Y. Nakashima, M. Ikeda, and K. Asada,
    "New method for calculating inductance on VLSI circuit and estimation of circuits by this method,"
    信学技法, VLD2000-50, SDM2000-123, pp.17-22, Sep. 2000,
  • H. Yamaoka, Y. Nakashima, T. Nezuka, and 小松 聡,
    "Designs in Asada-Ikeda Lab.,"
    VDEC LSI デザイナーズフォーラム 2000/ VDEC LSI Designers Forum 2000, Sep. 2000,
  • H. Yamaoka, M. Ikeda, and K. Asada,
    "A High-Speed PLA with Latch Sense Amplifiers,"
    Proc. of 4th Workshop on System VLSI in Biwako, pp.223-226, Nov. 2000,
  • K. Seto, H. Yoshida, M. Ikeda, and K. Asada,
    "Multi-Level Logic Optimization Using Node Complementation,"
    IEEE/ACM International Workshop on Logic Synthesis, U.S.A., pp.291-294, May. 2000,
  • T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
    "A Gray-Scale Image Sensor for Motion Detection and 3-D Measurement,"
    ロボティクスメカトロニクス講演会 Proceedings of JSME Conference on Robotics and Mechatronics, 1A1-50-069, May. 2000,
  • M. Hoshino, T. Nezuka, M. Ikeda, and K. Asada,
    "A 3-D Measurement System with a Smart Position Sensor,"
    DAシンポジウム Proceedings of DA Symposium, pp.133-138, Jul. 2000,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A Smart Image Sensor for Position Detection with a Quad-tree Scan Controller,"
    Proceedings of 4th Workshop on System VLSI in Biwako, pp.183-185, Nov. 2000,
  • T. Nezuka, J. Akita, M. Ikeda, and K. Asada,
    "A Smart Image Sensor with Novel Implementation of Quad-tree Scan,"
    Proceedings of the 2nd IEEE Asia-Pacific Conference on ASIC, pp.135-138, Oct. 2000,
  • T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
    "A Position Detection Sensor for 3-D Measurement,"
    Proceedings of the 26th European Solid-State Circuits Conference, pp.412-415, Sep. 2000,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Data Compression Encoding Method for High Throughput Data Transmission in VLSI,"
    Proc. of 4th Workshop on System VLSI in Biwako, pp.215-218, Nov. 2000,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Bus Data Encoding with Adaptive Code-book Method for Low Power IP Based Design ,"
    International Workshop on IP-Based Synthesis and SoC Design, Dec. 2000,
  • J. Qiao, M. Ikeda, and K. Asada,
    "Optimum Functional Decomposition for LUT-based FPGA Synthesis,"
    第13回 回路とシステム(軽井沢)ワークショップ (2000 IEICE, The 13th Workshop on Circuits and Systems) 2000 IEICE,, pp。119-124, Apr. 2000,
  • J. Qiao, M.Ikeda, and K.Asada,
    "Optimum Functional Decomposition for LUT-based FPGA Synthesis,"
    The 10th International Conference on Field-Programmable Logic and Applications, in Austria , pp.555-564, Aug. 2000,
  • M. Ikeda and K. Asada,
    "A New Trial on HDL Exercise Class for Undergraduate School in EE Department,"
    Proc. of 2000 European Workshop on Microelectronics Education(EWME 2000) in France, pp. 146--147, 2000,
  • K. Asada, H. Ochi, M. Ikeda, and K. Kobayashi,
    "Design and Fabrication of Digital LSI,"
    培風館, 全体141ページ, Jun. 2000,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Adaptive codebook encoding for low-power chip interface,"
    Electronics and Communications in Japan, Part Ⅱ-Electronics, Vol.83, pp.17-23, Jun. 2000,
  • M. Ikeda,
    "VDEC activities of these 3 years,"
    1999年電子情報通信学会総合大会, PA-2-1, pp. 527-528, Mar. 1999,
  • H. Ito and K. Asada,
    "Accuracy of device-parameter extraction method using S-factor characteristics in FD-SOI MOSFETs,"
    第46回応用物理学会関係連合講演会, 30p-ZM-9, Mar. 1999,
  • J. Qiao and K. Asada,
    "Multiple-output decomposition and its application to LUT-based FPGAs,"
    1999年電子情報通信学会総合大会, A-3-6, p. 110, Mar. 1999,
  • T. Yamashita and K. Asada,
    "High Speed Pass-transistor Logic with Capacitor separated sense amplifire,"
    1999年電子情報通信学会総合大会, C-12-16, p.114, Mar. 1999,
  • K. Seto, M. Ikeda, and K. Asada,
    "Logic Resynthesis of Standard Cell ICs using SPFDs for timing optimization,"
    情報処理学会全国大会, pp. 39-40, Mar. 1999,
  • H. Aoki, M. Ikeda, and K. Asada,
    "Circuit for Measuring Noise in VLSI Power Lines,"
    1999年電子情報通信学会総合大会, A-3-13, p. 117, Mar. 1999,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Direct Extraction of Capacitance Matrix in VLSI,"
    Proceeding of International Conference on Microelectronic Test Structures (ICMTS), pp.200-205, Mar. 1999,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method,"
    9th GREAT LAKES SYMPOSIUM ON VLSI, 9B.1, pp. 368-371, Mar. 1999,
  • T. Mido and K. Asada,
    "An Analysis on Hi-Frequenacy Interconnection in VLSI Considering Inductive Effects,"
    International Workshop on Timing Issues In the Specification and Synthesis of Digital Systems (TAU'99), pp.173-178, Mar. 1999,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A Motion Detection Image Sensor with Variable Block Access,,"
    Procedding of the 1999 IEICE General Conference, p.154, Mar., 1999., C-12-56, p.154, Mar. 1999,
  • K. Asada, T. Nezuka, T. Fujita, M. Ikeda, and J. Akita,
    "Image sensors with flexible access methods to pixels for adaptive spatial and time resolution,,"
    International Symposium on Future of Intellectual Integrated Electronics,, pp49-62, Mar. 1999,
  • K. Asada, T. Nezuka, ,T. Fujita, M. Ikeda, and J. Akita,
    "An Image Sensor for Motion Detection using Variable Block Access,"
    International Symposium on Future of Intellectual Integrated Electronics, ex.12, Mar. 1999,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
    IEICE Transactions on Electronics, Vol.E82-C, No.4, pp.570-575, Apr. 1999,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Adaptive Codebook Encoding for Low Power Chip Interface,"
    電子情報通信学会論文誌 , Vol.J82-C-II, No.4, pp.203-209 , Apr. 1999,
  • K. Asada,
    "VDEC:An Approach in Universities,"
    電子情報通信学会誌, Vol.82,No.5, pp。454-457, May. 1999,
  • K. Asada,
    (in Japanese) "VSACへの期待,"
    (社)日本電子機械工業会 システムLSI開発支援センター(VSAC), 1999,
  • T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
    "A Binary Image Sensor for Motion Detection,"
    Proceedings of JSME Conference on Robotics and Mechatronics, 1999,
  • M. Ikeda and K. Asada,
    "Standard Design Flows of Logic LSIs in Japanese Universities and VDEC,"
    Proc. of 1999 Micro Electronic Systems Education Conference (MSE 99), pp. 8-9, Jul. 1999,
  • M. Ikeda and K. Asada,
    "Standard Cell Library Generation and Standard Design Flow Establishment Through VDEC Chip Fabrication Pilot Project,"
    Proceding of '99 DA Symposium, pp. 149-152, Jul. 1999,
  • K. Seto, M. Ikeda, and K. Asada,
    "Logic Resynthesis using SPFDs for Standard Cell ICs,"
    DA Symposium '99, , Jul. 1999,
  • R. Hamada, S. Komatsu, M. Ikeda, and K. Asada,
    "Statistical Analysis of Data Sequences on Microprocessor Data Bus Lines and Proposal of Models for Artificial Data Sequences,"
    IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences, Vol.J82-A, No.8, pp.1406-1408, Aug. 1999,
  • H. Ito  and K. Asada,
    "Extraction Method of Structural Parameters Using Backgate Characteristics of Subthreshold Slope Factor in Fully-Depleted SOI MOSFETs,"
    電子情報通信学会論文誌 , Vol.J82-C-II, No.9, pp.498-504 , Sep. 1999,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
    IEICE Trans.,Electronics, Special Issue on International Conference on Microelectronic Test Structures, Apr. 1999,
  • S. Komatsu, K. Asada, and M. Ikeda,
    "Adaptive Codebook Encoding for Low Power Chip Interface,"
    電子情報通信学会論文誌C-II, Vol.J82-C-II, No.4, pp.203-209, Apr. 1999,
  • M. Aoyagi and K. Asada,
    "Vacancy Distribution in Aluminum Interconnection on Semiconductor Device,"
    Jpn.J.Appl.Physics, Part 1, No.4A, Vol.38(1999), p.1909-1914, Apr. 1999,
  • K. Asada,
    "Associative momory with minimum hammingdistance detector and its application to bus data encoding,"
    Proc. of AP-ASIC 99, 16.1, Aug. 1999,
  • M. Ikeda, H. Aoki, and K. Asada,
    "Voltage Bounce Testing in Power Supply Lines Using Onchip Voltage Scan Path,"
    Technical Report of IEICE., CPM99-121, ICD99-127, pp. 9-14, Dec. 1999,
  • M. Ikeda and K. Asada,
    "Standard Cell Library Generation and Standard Design Flow Establishment Through VDEC Chip Fabrication Pilot Project,"
    Proceding of '99 DA Symposium, pp. 149-152, Jul. 1999,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
    IEICE Transactions on Electronics, Vol.E82-C, No.4, pp.570-575, Apr. 1999,
  • T. Nezuka, M. Ikeda, and K. Asada,
    "A Gray-Scale Image Sensor for Sub-pixel Level Motion Detection and Stereo Vision,"
    Proceedings of 3rd Workshop on System VLSI in Biwako, pp.183-185, Nov. 1999,
  • K. Asada,
    "Microelectronics education in Japan,"
    Microelectronics Education 1998, Proceedings pp. 195-198, May. 1998,
  • K. Asada,
    "VDEC (VLSI Design and Education Center): The Center of VLSI Desigh Education in Japan,"
    MRS-J NEWS , Vol.10, No.2, pp.4-5, May. 1998,
  • K. Sekine, S. Nakai, T. Nishimura, K. Shimoi, K. Nishimura, and K. Asada,
    "Progress in Electronics, Information and System Engineering,"
    Journal of IEE of Japan, Vol.118, No.6, pp.348-354, Jun. 1998,
  • K. Asada, T. Nezuka, and M. Ikeda,
    "A High Speed CMOS Image Sensor with Hierarchical Access Path,"
    1998年電子情報通信学会ソサイエティ大会, SC-10-5,pp184-185, Sep. 1998,
  • T. Yamashita and K. Asada,
    "High Speed Pass-transistor Logic with Capacitor separated sense amplifire,"
    第2回システムLSI琵琶湖ワークショップ For the Interdisciplinary Materials Research, pp.233-235, Nov. 1998,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI,"
    Proceeding of International Conference on Microelectronic Test Structures (ICMTS) 110周年記念特集電気電子技術10年の歩み, pp.217-222, Mar. 1998,
  • K. Asada, T. Nezuka, and M. Ikeda,
    "A High Speed CMOS Image Sensor with Hierarchical Access Path,"
    1998年電子情報通信学会ソサイエティ大会講演論文集Proceedings of the 1998 Electronics Society Conference of IEICE, Pergamon, SC-10-5, p.184-185,, Sep. 1998,
  • Y. Sato, R. Zheng, and K. Asada,
    "Design of Pseudo Asynchronous Microprocessor with Completion Detection,"
    Technical Report of IEICE., ICD98-17, CPSY98-17, FTS98-17(1998-04) pp.47-52, Apr. 1998,
  • K. Asada, T. Nezuka, and J. Akita,
    "A Realization of Gray-scale Image Sensor with Quad Tree Scan,"
    平成9年度重点領域研究「極限集積化シリコン知能エレクトロニクス」公開シンポジウム, p202-208, Apr. 1998,
  • H. Ito and K. Asada,
    "Non-destructive Extraction of Structural Parameters of Fully-depleted SOI MOSFETs using Subthreshold Slope Characteristics,"
    1998 Conference on Optolectronics and Microelectronics Materials and Devices, Dec. 1998,
  • R. Zheng and K. Asada,
    "A High Speed Completion Prediction Adder Based on Binary Carry Lookahead Adder,"
    Proceeding of International Workshop on IP Based Synthesis and System Design, Grenable , Dec. 1998,
  • M. Ikeda and K. Asada,
    "CAM Macro Cells with Minimum Distance Detector using Time-Domain Technique,"
    International Workshop on IP Based Synthesis and System Design , pp.134-140, Dec. 1998,
  • T. Nezuka, M. Ikeda, and K. Asada,
    " A Gray-Scale Image sensor with Hierarchical Access Path ,"
    2nd Workshop on System LSI in Biwako, p.227-230, Dec. 1998,
  • T. Nezuka, J. Akita, and K. Asada,
    "A CMOS Image Sensor for Motion Detection with Hierarchical Scan,"
    Procedding of the 1998 IEICE General Conference, C-12-49, p.177, Mar. 1998,
  • M.Aoyagi and K.Asada ,
    "Vacancy distribution in aluminum interconnection on semiconductor device,"
    Ext. Abstr. (45th Spring Meet.1998); Japan Society of Applied Physics and Related Societies,, 29p-N15.(in Japanese), Mar. 1998,
  • M. Song and K. Asada,
    "Design of Low Power Digital VLSI Circuits Based on a Novel Pass-transistor Logic,"
    IEICE Trans. Electronics, Vol.E81-C, No.11, pp.1740-1749, Nov. 1998,
  • T. Nezuka and K. Asada,
    "An Image Sensor for Motion Compensation with Hierarchical Scan,,"
    Technical Report of IEICE., DSP98-95, pp.43-48, Oct., 1998., Vol.98,No.318,DSP98-95,p.43-48, Oct. 1998,
  • T. S. Cheung and K. Asada,
    "Regenerative Pass-Transistor Logic: A Modular Circuit Technique for High Speed Logic Circuit Design,"
    IEICE Trans. on Electronics , Vol.E-79C, No.9, pp.1274-1284, Sep. 1998,
  • R. Zheng and K. Asada,
    "Design of Completion Prediction Adder with Shift Operation and Its Aoolication to Microcessor ,"
    通信学会、信学技報, VLD98-51, pp.51-56, Sep. 1998,
  • R. Zheng and K. Asada,
    "Design of a Completion Adder,"
    通信学会全国大会講演論文集, C-12-22, pp.113, Sep. 1998,
  • T. Mido, H. Ito, and K. Asada,
    "TEST Structure for Direct Extraction of Capacitance Matrix in VLSI,"
    1998 IEICE Fall Conference, C-12-1, pp.92, Sep. 1998,
  • H. Ito and K. Asada,
    "TEST Structure for Direct Extraction of Capacitance Matrix in VLSI,"
    1998年電子情報通信学会ソサイエティ大会, C-12-1, pp.92, Sep. 1998,
  • M. Ikeda and K. Asada,
    "Time-Domain Minimum-Distance Detector and Its Application to Low Power Coding Scheme on Chip Interface,"
    24th European Solid State Circuit Conference, pp.464-467, Sep. 1998,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Adaptive Code-Book Encoding for Low Power Chip-Interface,"
    通信学会、信学技報, ICD98-176, pp.1-6, Sep. 1998,
  • M.Aoyagi and K.Asada,
    "Analysis of aluminum interconnection life time due to stress-induced migration on semiconductor device,"
    Ext.Abstr. (59th Fall Meet.1998); Japan Society of Applied Physics and Related Societies, 16p-ZL5.(in Japanese), Sep. 1998,
  • T. Mido and K. Asada,
    "An Evaluation of Skin Effect on Hi-Frequency VLSI Interconnections using Numerical Simulation,"
    第45回応用物理学会関係連合講演会. , 28p-L-8, p.11, Oct. 1998,
  • T. Mido and K. Asada,
    "An Analysis on Hi-Frequency Interconnections in VLSI Considering Skin Effect,"
    通信学会VLSI設計研究会、信学技報, VLD98-84、Vol.98、No.2 pp.89-94, Oct. 1998,
  • H. Ito and K. Asada,
    "Device parameter extraction using subthreshold slope factor characteristics in SOI MOSFETs,"
    第59回応用物理学会学術講演会, 15a-P9/II p.778, Oct. 1998,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Adaptive Code-Book Encoding for Low Power Chip-Interface,"
    1998年電子情報通信学会ソサイエティ大会, C12-23, pp.114, Oct. 1998,
  • M. Aoyagi and K. Asada,
    "Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductort Device,"
    Jpn.J.Appl.Physics, Vol.36, Part 1, No.5A, pp.2601-2605, May. 1997,
  • M. Ikeda, Y. Tajima, and K. Asada,
    "Partitioned and Pipelined Bus Architecuture in VLSI,"
    Techniclal Report of IEICE 信学技報, ICD97-4, CPSY97-4, FTS97-4, pp.25-32, Apr. 1997,
  • R. Zheng , M. Ikeda, and K. Asada,
    "A Case Study: Design and Implementation of Pseudo-Asynchronous ,"
    International Workshop on Logic and Architecture Synthesis '97 , Dec. 1997,
  • K. Hoh, K. Ueda, T. Nanya, H. Yasuura, A. Iwata, N. Ieda, Y. Ishii, and K. Asada,
    "VLSI Design Education in Japan,"
    Technical Report of the Journal IEICE, Vol.80, No.1, pp.40-62, Jan. 1997,
  • T. Mido and K. Asada,
    "Crosstalk Noise in High Density and High Speed Interconnections due to Inductive Coupling,"
    Proceeding of ASP-DAC'97, pp.215-220, Jan. 1997,
  • K. Asada and K. Hoh,
    "VLSI Design and Education Center (VDEC) Current status and future plan,"
    Proceed. of the Asia and South Pacific Design Automation Conference 1997 (ASP-DAC '97), pp.365-369,Jan.28-31,1997, Makuhari Messe, Jan. 1997,
  • K. Asada and K. Hoh,
    "VLSI Design and Education Center (VDEC) Current status and future plan,"
    Proceeding of ASP-DAC'97, pp.365-369,Jan.28-31,1997, Makuhari Messe, Jan. 1997,
  • J. Akita and K. Asada,
    "An Image Scanning Method with Selective Activation of Tree Structure,,"
    IEICE Trans. on Electronics, Vol.E80-C, No.7, pp.956-961, , Jul. 1997,
  • M. Song and K. Asada,
    "Power Optimization for Data Compressors Based on a Window Detector in a 54 x 54 Bit Multiplier,"
    IEICE Trans. on Electronics , Vol.E80-C, No.7, pp.1016-1024, Jul. 1997,
  • T. S. Cheung and K. Asada,
    "Design Automation Algorithms for Regenerative Pass-transistor Logic,"
    ISCAS (International Symposium on Circuits and Systems), Vol.3 (Cad VLSI) pp.1540-1543, Jun. 1997,
  • J. Akita and K. Asada,
    "An Image Sensor using Quad Tree for Selective Scanning with Adaptive Resolution,"
    1997 IEEE CCD&AIS Workshop, Jun. 1997,
  • R. Ikeno, H. Ito, and K. Asada,
    "Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects,"
    IEICE Trans. on Electronics, Vol.E80-C, No.6, pp.806-811, Jun. 1997,
  • T. Mido and K. Asada,
    "An Analysis of Current Distribution in Finit Width Interconnection in Hi-Frequency Intergrated System,"
    回路実装学会 実装CAE研究会、研究報告, CAE97-1, Jun. 1997,
  • T. S. Cheung and K. Asada,
    "High-speed high-density adders and multiplier design using Regenerative Pass-transistor Logic,"
    IEICE Trans. on Electronics, Vol.E80-C, No.3, pp.478-488, Mar. 1997,
  • T. Mido, M. Ikeda, and K. Asada,
    "Bus Data Coding with Low Coupled Signal for Low Power VLSI,"
    電子情報通信学会 VLSI設計研究会, VLD96ー108、PP.91-96, Mar. 1997,
  • K. Asada and J. Akita,
    "Image Sensor using Tree Structure ,"
    重点領域研究「知能の極限集積化」特別公開シンポジウム(Symposium on Scientific Research on Priority Arears, "Ultimate Integration of Intelligence on Silicon Electronic Systems"), Mar. 1997,
  • T. Mido and K. Asada,
    "An Analysis on Hi-Frequency VLSI Interconnections Considering Skin Effect,"
    第44回応用物理学会関経連合講演会, 28pーBー4, Mar. 1997,
  • M. Ikeda and K. Asada,
    "Bus Data Coding for Low Power Chip Interface,"
    1997年電子情報通信学会総合大会, C-12-47, Mar. 1997,
  • J. Akita and K. Asada,
    "Image Data Compression Efficiency using Tree Scanning and Run-length Coding,"
    電子情報通信学会春季全国大会, A-6-10, Mar. 1997,
  • H. Ito and K. Asada,
    "Minimum propagation delay and optimum of LDD Length in 0.1um MOSFET,"
    第44回応用物理学会関経連合講演会, 29p-H-14, Mar. 1997,
  • S. Komatsu, M. Ikeda, and K. Asada,
    "Comparative Study on Bus Architecture and Multiplexer Architecture for Low Power Microprocessor,"
    電子情報通信学会春季全国大会, Cー12ー46, Mar. 1997,
  • T. Torii and K. Asada,
    "A Study of Selector Based Logic Circuit Design,"
    電子情報通信学会春季全国大会, A-3-15, Mar. 1997,
  • R. Zheng and K. Asada,
    "A Case-Study on Architecture and Mapping of EPGA: Implementation of A Microprocessor,"
    電子情報通信学会春季全国大会, C-12-7, Mar. 1997,
  • Y. Sato and K. Asada,
    "A Design of Completion Detection Pipelined Adder,"
    電子情報通信学会春季全国大会, Cー12ー39, Mar. 1997,
  • J. H. Lee and K. Asada,
    "Input Data Dependence in Synchronous Completion Prediction Adder,"
    電子情報通信学会春季全国大会, Cー12ー41, Mar. 1997,
  • T. Yamashita and K. Asada,
    "Signal Recover Circuit with a Latch Sense Amplifier for CPL,"
    電子情報通信学会春季全国大会, Cー12ー49, Mar. 1997,
  • M. Aoyagi and K. Asada,
    "Experimental study of annealing effect on formation in aluminum interconnection,"
    The 44th Spring Meeting, Japan Society of Applied Physics and Related Societies, 29a-PC19, Mar. 1997,
  • R. Ikeno, H. Ito, and K. Asada,
    "SOI Device Parameter Estimation with 2-dimensionally Quantized Mobility Modeling in Electron Inversion Layer,"
    第44回応用物理学会関経連合講演会, Mar. 1997,
  • J. H. Lee and K. Asada,
    "A Synchronous Completion Prediction Adder(SCPA),"
    IEICE Trans. on Fundamental of Electronics, Communications and Computer Sciences, Vol.E-80A, No.3, pp.606-609, Mar. 1997,
  • T. S. Cheung and K. Asada,
    "Design of High-speed High-density Parallel adders and multiplier using Regenerative Pass-transistor Logic,"
    IEICE Trans. on Electronics, Vol.E-89-C, No.3, pp.478-488, Mar. 1997,
  • J. H. Lee and K. Asada,
    "A Synchronous Completion Prediction Adder (SCPA),"
    IEICE Trans. Fundamentals, Vol.E80-A, No.3, pp.606-609, Mar. 1997,
  • K. Asada, J. Akita, and R. Watabe,
    "A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
    Computers & Electrical Engineering, Vol.23, No.6, pp.453-461, Nov. 1997,
  • R. Zheng, M. Ikeda, J. H. Lee, and K. Asada,
    "Design and Implementation of A Pseudo-Asynchronous Microprocessor,"
    1997年電子情報通信学会秋期大会 , C12-22, , Sep. 1997,
  • K. Asada, M. Aoyagi, and T. Mido,
    "An Analysis on Hi-Frequency Interconnections in VLSI Considering,"
    電子情報通信学会 VLSI 設計研究会, 信学技報, VLD97-69, Vol.96, No.269,, Sep. 1997,
  • J. H. Lee and K. Asada,
    "A synchronous completion prediction adder(SCPA) with high hardware-delayh performance,"
    7th International Symposium on IC Technology, Systems & Applications (ISIC-97 ), pp. 60-63, , Sep. 1997,
  • K. Nose, R. Ikeno, and K. Asada,
    "Simulation Study on Extraction Mechanism of Generated Holes in the Floating-body SOI MOSFETs,"
    Technical Report of IEICE,信学技報 Singapore, 9/10-12, Sep. 1997,
  • K. Asada, H. Ito, and T. Mido,
    "Test Structure for Calculating Capacitance Matrix of Multi Conductors in VLSI,"
    1997年電子情報通信学会秋期大会, C-12-5, P.88, Sep. 1997,
  • J. Akita and K. Asada,
    "A CMOS Image Sensor with Variable Block Access Function for Adaptive Resolution Scan、,"
    1997年電子情報通信学会秋季大会, C12-39, Sep. 1997,
  • T. Mido and K. Asada,
    "Delay-Optimum Aspect Ratio of VLSI Interconnections based on New Accurate Capacitance Formulations,"
    European Conference on Circuit Theory and Design '97, Vol.2, pp.978-983, Sep. 1997,
  • K. Hoh and K. Asada,
    "Chip fabrication for VLSI design education ,"
    Technical Report of 応用物理, Vol.66, No.8, pp.858-861, 1997,
  • T. Mido and K. Asada,
    "Delay Model for Microstrip Lines Considering Skin Effect for Over 1GHz Operation,"
    回路実装学会 第8回ワークショップ, Nov. 1996,
  • M. Ikeda, J. H. Lee, R. Zheng, and K. Asada,
    "Power Reduction and Performance Improvement in VLSIs,"
    電子情報通信学会 LSI設計技術の未来を考える琵琶湖ワークショップ ポスター発表, pp.41-45, Nov. 1996,
  • M. Aoyagi and K. Asada,
    "Initial stage of stress-migration phenomenon in aluminum interconnection on semiconductor device,"
    Technical Report of IEICE, SDM96-132,, Vol.96, No.360, pp.1-7 , Nov. 1996,
  • T. Mido and K. Asada,
    "Delay Model for Mictostrip Lines Considering Skin Effect for Over 1GHz Operation,"
    JIPC 8th Workshop, Nov. 1996,
  • K. Asada and J. Akita,
    "A Tree Structure of Automata for Selective Image Scanning and Its Implementation ,"
    4th Int'l Conf.of Soft Computing (IIzuka'96 ) , A-4-1, Oct. 1996,
  • R. Ikeno and K. Asada,
    "Optimum Design of Device Parameters for Switching Energy Minimization using Circuit Simulation,"
    電子情報通信学会 論文誌(C-II) , vol.J79-C-II, No.10,pp.525-526, Oct. 1996,
  • T. Mido and K. Asada,
    "Accurate Capacitance Formulas for VLSI Interconnections Based on Finite Element Analysis,"
    Proceedings of ANSYS'96 Conference in Japan, pp.239-245, Oct. 1996,
  • T. S. Cheung and K. Asada,
    "Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design,"
    IEICE TRANS. ELECTRON.,, Vol.E79-C, No.9, pp.1274-1284, Sep. 1996,
  • T. Mido and K. Asada,
    "New Capacitance Formulation and Delay Optimum Aspect Ratio for VLSI Interconnections,"
    電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96-49,Vol.96, No.259, pp.55-60, Sep. 1996,
  • S. Komatsu, R. Ikeno, H. Ito, and K. Asada,
    "Design parameter dependence and optimization of drain characteristics of DTMOS,"
    電子情報通信学会 VLSI設計研究会、通信学会技術報告, VLD96ー43,Vol.96,No.259, Sep. 1996,
  • M. Ikeda and K. Asada,
    "Signal Transition Oriented Placement and Routing for Power Reduction,"
    電子情報通信学会ソサイエティ大会, SA-2-4, Sep. 1996,
  • J. H. Lee and K. Asada,
    (in Japanese) "同期式完了予測型加算機,"
    電子情報通信学会ソサイエティ大会, C-504, Sep. 1996,
  • R. Ikeno and K. Asada,
    "Device Dependent Convergence-ability of Matrix Solution in Device Simulation,"
    第57回応用物理学会学術講演会, 7a-V-4, Sep. 1996,
  • T. Mido and K. Asada,
    "Formulation for Three Dimensional Capacitances of Contiguous Interconnections in VLSI,"
    1996年電子情報通信学会秋期大会, C-470、p.131, Sep. 1996,
  • K. Asada and T. Mido,
    "Optimum Aspect Ratio of Cross Section of VLSI Interconnections Considering RC-Delay,"
    1996年電子情報通信学会秋期大会, C-471,p,132, Sep. 1996,
  • T. Torii and K. Asada,
    "A Study of Input Selected Logic Circuit Design Based on Human Procedure,"
    電子情報通信学会ソサイエティ大会, A-53, Sep. 1996,
  • T. Yamashita and K. Asada,
    "An Application of a Latch Sense Amplifier for CPL,"
    電子情報通信学会ソサイエティ大会, C-476, Sep. 1996,
  • J. Akita and K. Asada,
    "An Implementation of Image Scanning Method with Selective Activation of Tree Structure,"
    1996年電子情報通信学会秋期大会, A-54, Sep. 1996,
  • K. Asada and J. Akita,
    "A Selective Image Scanning Method using Tree Structure of Automata and Its Applications,"
    1996年電子情報通信学会秋期大会, ES-3-7, Sep. 1996,
  • M. Aoyagi and K. Asada,
    "Effect of residual stress on stress-migration lifetime in Aluminum interconnection,"
    The 57th Fall Meeting, Japan Society of Applied Physics and Related Societies, 8p-N16, Sep. 1996,
  • R. Ikeno and K. Asada,
    "Robust simulation for the hysteresis phenomena of SOI MOSFET's by Quasi-Transient Method,"
    1996 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'96), P-13, Sep. 1996,
  • M. Ikeda, J. H. Lee, T. Zhang, and K.Asada,
    "Power Reduction and Performance Improvement in VLSIs,"
    1996 IEICE Biwako Workshop, pp.41-45, Sep. 1996,
  • S. Suzuki, M. Fujishima, M. Tsuchiya, and K. Asada,
    (in Japanese) "学部3年後期実験におけるCMOSゲートアレイの作製,"
    東京大学工学部・工学系研究科紀要, A-34、pp.96-97, 1996,
  • M. Ikeda and K. Asada,
    "Bus Data Coding with Zero Suppression for Low Power Chip Interface,"
    IFIP International Workshop on Logic and Architecture Synthesis, pp.267-274, Dec. 1996,
  • H.Ito and K.Asada,
    "Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate,"
    IEICE Trans. on Electronics, Vol.E79-C,No.2, pp.185-191, Feb. 1996,
  • 三堂 哲寿 and 浅田 邦博,
    "Crosstalk Noise Considering Inductive Coupling in Strip Wires in Heterogeneous Insulators,"
    回路実装学会 第7回ワークショップ, Jan. 1996,
  • 渡部 亮太, 秋田 純一, and 浅田 邦博,
    "An Implementation on CMOS Circuit of Tree Structure of Automata for Image Scanning,"
    1996年テレビジョン学会年次大会, 3ー6, Jul. 1996,
  • 秋田 純一, 渡部 亮太, and 浅田 邦博,
    "A Novel Tree Structure of Automata for Selective Scanning of Image Signals,"
    1996年テレビジョン学会年次大会, 1996/03/07, Jul. 1996,
  • Makoto Ikeda and K. Asada,
    "Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
    IEICE Transaction on Electronics, Vol.E79-C,No.3, pp.424-429, Mar. 1996,
  • Makoto Ikeda and K. Asada,
    "Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors,"
    IEICE Trans. Electron, Vol.E79-C, No.3, pp, Mar. 1996,
  • 池野 理門, 伊藤 浩, 名倉 徹, and 浅田 邦博,
    "Evaluation of SOI MOSFET Threshold Voltage using 1-D Device Simulation,"
    電子情報通信学会 シリコン材料・デバイス研究会、SDM94-208、, Mar. 1996,
  • 浅田 邦博 and 秋田 純一,
    "Intelligent Low Power Device and Circuit,"
    重点領域研究「知能の極限集積化」特別公開シンポジウム, Mar. 1996,
  • 池田 誠 and 浅田 邦博,
    "Power Reduction using Variable-Width Scheme in Adder,"
    96 電子情報通信学会総合大会, pp.C-555, Mar. 1996,
  • 秋田 純一 and 浅田 邦博,
    "Image Scanning Method with Data Compression Using Tree Structure of Automata,"
    電子情報通信学会春季全国大会, Mar. 1996,
  • 三堂 哲寿 and 浅田 邦博,
    "Simulation of VLSI Interconnections Considering Inductive Coupling Crosstalk Noise,"
    第43回応用物理学会関係連合講演会シンポジウム講演, Mar. 1996,
  • 張 子誠 and 浅田 邦博,
    "A 3.3ns 8x8 bit Parallel Multiplier Using Regenerative Pass-transistor Logic,"
    電子情報通信学会 1996年全国春季大会, Mar. 1996,
  • 池野 理門 and 浅田 邦博,
    "Stable Solution for SOI MOSFET Simulation by Quasi-Transient Method,"
    第43回応用物理学会関係連合講演会, Mar. 1996,
  • 池田 誠 and 浅田 邦博,
    (in Japanese) "ビット幅可変方式を用いた加算機による消費電力削減,"
    電子情報通信学会総合大会, C-555, Mar. 1996,
  • 池野 理門 and 浅田 邦博,
    (in Japanese) "準過渡解析手法によるSOI MOSFETシミュレーションの安定解法,"
    第43回応用物理学会関係連合講演会, 26p-H-3, Mar. 1996,
  • 三堂 哲寿 and 浅田 邦博,
    (in Japanese) "集積回路内の相互接続配線における誘導性を考慮した伝送線路シミュレーッション,"
    第43回応用物理学会関係連合講演会, 26p-H-11, Mar. 1996,
  • 小松 聡, 池野 理門, 伊藤 浩, and 浅田 邦博,
    (in Japanese) "DTMOSのドレイン電流特性のデザインパラメータ依存性,"
    第43回応用物理学会関係連合講演会, 26p-H-4, Mar. 1996,
  • 鄭 若丹, 池田 誠, and 浅田 邦博,
    "A Synchronous Completion Prediction Adder (SCPA),"
    電子情報通信学会総合大会, Cー554, Mar. 1996,
  • 鈴木真一, 藤島 実, 土屋 昌弘, and 浅田 邦博,
    (in Japanese) "学部3年後期実験におけるCMOSゲートアレイの作製,"
    東京大学工学部・工学系研究科紀要, A-34、pp.96-97, 1996,
  • 池田 誠, 李 知漢, and 浅田 邦博,
    "Power Reduction and Performance Improvement in VLSIs,"
    IEICE 琵琶湖ワークショップ, pp.41-45, 1996,
  • 池野 理門, 名倉 徹, and 浅田 邦博,
    "Estimation of SOI MOSFET Threshold Voltage Using 1-D Device Simulation Method,"
    第42回応用物理学関係連合講演会, Mar. 1995,
  • 池野 理門, 伊藤 浩, 名倉 徹, and 浅田 邦博,
    "Evaluation of SOI MOSFET Threshold Voltage using 1-D Device Simulation,"
    電子情報通信学会 シリコン材料・デバイス研究会, SDM94-208, Mar. 1995,
  • 伊藤 浩 and 浅田 邦博,
    "Leak Current Characterization in high Frequency Operation of CMOS/SOI Circuits,"
    第42回応用物理学会関係連合講演会, Mar. 1995,
  • 張 子誠 and 浅田 邦博,
    "A Low Power Digital Design Technique,"
    1995年電子情報通信学会 春季全国大会, Mar. 1995,
  • J. Akita and K. Asada,
    "An Estimation of State Code Assignment for Low Power Finite State Circuit,"
    1995年電子情報通信学会 春季全国大会, A-108, pp.108, Mar. 1995,
  • K. Asada, M. Ikeda, and J. Akita,
    "VLSI Design with Verilog HDL,"
    1995年電子情報通信学会 春季全国大会, GD-2-6, Mar. 1995,
  • 池田 誠 and 浅田 邦博,
    "Power Optimization Method for Partitioned Bus Architecture,"
    1995年電子情報通信学会 春季全国大会, Mar. 1995,
  • 浅田 邦博 and 池田 誠,
    "Design of General Purpose Microprocessor using Partitioned Bus Architecture,"
    1995年電子情報通信学会 春季全国大会, Mar. 1995,
  • 名倉 徹, 池野 理門, and 浅田 邦博,
    "Analytical Model for Back Gate Effect on SOI Device,"
    第42回応用物理学関係連合講演会, Mar. 1995,
  • 池野 理門 and 浅田 邦博,
    "Optimization of VLSI Process Parameters Using Circuit Simulation,"
    1995年電子情報通信学会 春季全国大会, Mar. 1995,
  • H. Ito and K. Asada,
    "Leak Current Characterization in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate,"
    IEEE Proc. International Conference on Microelectronics Test Structure, Mar. 1995,
  • K. Asada and J. Akita,
    "A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
    IEICE Trans. on Electronics, Vol.E78-C, No.4, pp.436-440, Apr. 1995,
  • 池野 理門, 伊藤 浩, and 浅田 邦博,
    "Device Parameter Estimation by 1-D SOI Simulation Considering 2-D Quantum Effects,"
    第56回応用物理学会学術講演会, 27a-ZQ-3, Aug. 1995,
  • Minkyu Song and K. Asada,
    "Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54 x 54 Bit Multiplier,"
    IEEE International Conference on Circuits and Systems (ISCAS'95) /IEEE Trans. Circuits Syst., pp.1568-1571, 1995,
  • T. S. Cheung, K.Asada, K.L.Yip, and Y.C.Cheng,
    "Low Power CMOS Digital Circuit Design with Reduced Voltage Swing,"
    Proc.IEEE TENCON '95, pp.311-314, Nov. 1995,
  • T. S. Cheung and K.Asada,
    "Clock Separated Logic:A Double-Rail Latch Circuit Technique for High Speed Digital Design,"
    Proc.IEEE TENCON '95 IEEE Region 10 Conf.on VLSI, pp.303-306, Nov. 1995,
  • R.Ikeno, H.Ito, and K.Asada,
    "One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects,"
    Special Issue on Computational Electronics,The Fourth International Workshop on Computational Electronics (IWCE-4), Gordon & Breach Science Publishers, pp.65-67, Nov. 1995,
  • Makoto Ikeda and K. Asada,
    "Data Bypassing Register File for Low Power Microprocessor,"
    IEICE Transaction on Electronics, Vol.E78-C, No.10, pp.1470-1472, Oct. 1995,
  • R. Ikeno, H.Ito, and K.Asada,
    "One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects,"
    4th International Workshop on Computational Electronics, P11, Oct. 1995,
  • 秋田 純一 and 浅田 邦博,
    "A Signal Scanning Method of Sensors with Hierarchal Structure of Node Automata,"
    電子情報通信学会 技術報告, Vol.95. pp.71-78, Sep. 1995,
  • 三堂 哲寿 and 浅田 邦博,
    "Crosstalk Noise Considering Inductive Coupling in VLSI Interconnections in Heterogeneous Insulators,"
    電子情報通信学会 VLSI設計研究会、通信学会技術報告, Vol.95,No.232,pp.69-74, Sep. 1995,
  • Christoph Wasshuber and K. Asada,
    "Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages,"
    Jpn.J.Appl.Phys. , Vol.34(1995), PP.l1230-l1233, Part 2, No.9B, Sep. 1995,
  • 池田 誠, 李 知漢, and 浅田 邦博,
    "Design of Pseudo Asynchronous Microprocessor Using Synchronous Completion Detection Adder,"
    電子情報通信学会 集積回路設計研究会, ED95-87, pp.95ー100, Sep. 1995,
  • Y. Iwasaki and K. Asada,
    "Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator,"
    IEICE Trans. Fundamentals, Vol.E77-A, No.2, pp.371-379, Feb. 1994,
  • J. Akita and K. Asada,
    "A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
    EDAC-ETC Euro Asic 1994, Feb. 1994,
  • M. Lee and K. Asada,
    "Ultimate Lower Bound of Power for MOS Integrated Circuits,"
    Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
  • R. Ikeno and K. Asada,
    "High-Speed Method for Device Simulations by Block Division,"
    The Japan Society of Applied Physics, Mar. 1994,
  • M. Lee and K. Asada,
    "Ultimate Lower Bound of power for MOSFET Integrated Circuits,"
    Silicon Materials and Device Research Meeting (SDM), Mar. 1994,
  • M. Lee and K. Asada,
    "A proposal to evaluate switching Energy of Recycled Mechanism of a Device,"
    Proceedings of the 1994 IEICE Spring Conference, SC-7, Mar. 1994,
  • M. LEE and K. Asada,
    "A Proposal to Evaluate Minimum Switching Energy of Recycled Mechanism of MOS Device,"
    IEICE Spring Conference, SC-7, Mar. 1994,
  • 張 子誠, 宋 敏圭, and 浅田 邦博,
    "An Architectural Self-Refreshable Analog Memory System,"
    1994年電子情報通信学会 春季大会, Mar. 1994,
  • M. Ikeda and K. Asada,
    "A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in ULSIs,"
    The European Design and Test Conference 1994, Proceedings pp. 546-550, Mar. 1994,
  • K-R. Cho, K. Okura, and K. Asada,
    "Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM),"
    IEICE Trans. on Electronics, Vol.E77-C, No.4, Apr. 1994,
  • M. Ikeda and K. Asada,
    "A Power Reduction Method using Partitioned Bus Architecture in High-Level VLSI Design ,"
    IFIP Workshop on Logic and Architecture Synthesis, pp.225-230, Dec. 1994,
  • K. Asada and J. Akita,
    "Optimum State Assignment for CMOS Implementation of Low Power Finite State Machine,"
    IFIP Workshop on Logic and Architecture Synthesis, pp.141-146, Dec. 1994,
  • K. Asada and M. Lee,
    "Ultimate Lower Bound of Power for MOS Integrated Circuits and their Applications,"
    IEICE Trans. on Electronics, Vol.E77-C, No.7, pp.1131-1137, Jul. 1994,
  • T. S. Cheung and K. Asada,
    "A Single-Phase Clock Complementary Circuit Technique for Low Power Logic Circuit Design,"
    Proc. ASICON 1994, Beijing, China, No.4.20, pp.275-278, Oct. 1994,
  • H. Zhang, K. Asada, and T. S. Cheung,
    "A Layout Design Method of High Speed CMOS VLSIs for Minimizing Power Consumption,"
    Proc. ASICON 1994, Beijing, China, No.4.38, pp.348-351, Oct. 1994,
  • T. S. Cheung, M. K. Song, and K. Asada,
    "A Self-Refreshable Analog Memory Using Window Detector,"
    Proc. ASICON 1994, Beijing, China, No.3.3, pp.145-148, Oct. 1994,
  • 池田 誠 and 浅田 邦博,
    "A Power Consumption Reduction Method using Partitioned and Reduced-Swing Bus Lines in High-Level Syntesis ,"
    1994年電子情報通信学会 秋季全国大会, A-69, Sep. 1994,
  • 張 子誠 and 浅田 邦博,
    "High Speed CMOS Logic Circuit Design using Sub-Vdd Interfacing Technique,"
    1994年電子情報通信学会 秋季大会, SC-9-5, pp.243-4, Sep. 1994,
  • 張 子誠, 李 知漢, and 浅田 邦博,
    "A 100MHz Serial Data Synchronizer Using Clock Separated Logic Blocks,"
    1994年電子情報通信学会 秋季全国大会 , C-483 pp.161, Sep. 1994,
  • 伊藤 浩, 池田 誠, and 浅田 邦博,
    "Measurement of Fringing Capacitance with Ring Oscillator in MOS/SOI Device,"
    第55回応用物理学会学術講演会, 19p-ZG-5, Sep. 1994,
  • H. Hayashi and J. Akita,
    "A Method of Optimal State Code Assignment for Reducing Power Consumption in Synchronous Circuits,"
    1994年電子情報通信学会 秋季全国大会, A-67, pp.67, Sep. 1994,
  • J. Akita, H. Hayashi, and K. Asada,
    "An Estimation and Reduction of Power Consumption in Clock Line of Synchronous Flip-Flops,"
    1994年電子情報通信学会 秋季全国大会, A-68, pp.68, Sep. 1994,
  • H. Zhang and K. Asada,
    "A General and Efficient Mask Pattern Generator For Non-Series-parallel CMOS Transistor Network in "Synthesis for control dominated circuits","
    Edited by G. Saucier, Elsevier Science Publishers BV., 1993,
  • M. Fujishima, K. Asada, Y. Omura, and K. Izumi,
    "Low-power 1/2 Frequency Dividers Using 0.1μm CMOS Circuits Built with Ultrathin SIMOX Substrates,"
    IEEE Journal of Solid-State Circuits, Vol.28, No.4, pp.510-512, Apr. 1993,
  • M. Lee and K. Asada,
    "A High Performance on CMOS/SOI Integrated Circuits with SIMOX Substrates,"
    36th Midwest Symp. on Circuits and Systems (MWSCAS), Aug. 1993,
  • M. Lee, M. Fujisahima, and K. Asada,
    "A High Speed and Low Power on CMOS/SOI Technology,"
    51st Device Research Conference (DRC), Session ⅡA, No.8, Jun. 1993,
  • M. Lee, M. Fujishima, and K. Asada,
    "Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
    Proceedings of the 1993 IEICE Spring Conference, C-9, pp.5-203, Mar. 1993,
  • M. Fujishima and K. Asada,
    "Proposal of Standard Characterization Method for Dynamic Circuit Performance,"
    Proc. IEEE Int. Conf. on Microelectronic Test Structure , Vol.6, pp.227-232, Mar. 1993,
  • M. Lee, M. Fujishima, and K. Asada,
    "Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
    1993年電子情報通信学会 春季全国大会(IEICE), C-573, Vol.5, pp.203, Mar. 1993,
  • M. Lee and K. Asada,
    "Sub-100nm CMOS/SIMOX Delay Modeling by Time-Dependent Gate Capacitance Model,"
    1993 Int. Symp. on VLSI Tech., Systems, and Appl., pp.242-246, 1993,
  • H. Zhang and K. Asada,
    "An Improved Algorithm of Transistors Pairing for Compact Layout of Non-series-parallel CMOS Networks,"
    IEEE Proc. Custom Integrated Circuits Conf., pp.17.2.1-17.2.4, 1993,
  • M. Ikeda and K. Asada,
    "A proposal of high speed and low power data transmission method for VLSIs by reduced-swing signal,"
    IEICE Transaction on Electronics, E76-A No.10 pp1666-1675, Oct. 1993,
  • M. Lee and K. Asada,
    "Deep-Submicron CMOS/SIMOX Delay Modeling by Time-Dependent Capacitance Model,"
    IEEE Trans. on Electron Devices , Vol.40, No.10, pp.1897-1901, Oct. 1993,
  • M. Lee and K. Asada,
    "A New proposal for Delay Improvement on CMOS/SOI Future Technology,"
    IEICE Trans. on Electronics, Vol.E76-C, No.10, pp.1513-1522, Oct. 1993,
  • M. Fujishima and K. Asada,
    "A Nonpinchoff Gradual Channel Model for Deep-Submicron MOSFET's,"
    IEEE Trans. on Electron Devices, Vol.40, No.10 pp.1883-1885, Oct. 1993,
  • R. Ikeno and K. Asada,
    "High-Speed Method for Device Simulations by Area Division,"
    The Japan Society of Applied Physics, Sep. 1993,
  • M. Lee and K. Asada,
    "A Newly proposed for Delay Improvement on CMOS/SOI Future Technology,"
    SISDEP 93, Vol.5, pp.349-352, Sep. 1993,
  • 佐藤 純一 and 浅田 邦博,
    (in Japanese) "パルテノンによるRISCプロセッサの設計ーケーススタディー,"
    パルテノン研究会, Oct. 1993,
  • 張 洪明 and 浅田 邦博,
    "A Transistor pairing method for complex gate CMOS networks,"
    1993年電子情報通信学会 春季全国大会, A-95, pp.1-95, Mar. 1993,
  • 池田 誠 and 浅田 邦博,
    "Reduced Voltage Bus Lines using Termination Resistors,"
    1993年電子情報通信学会 春季全国大会, C-572, pp.5-202, Mar. 1993,
  • 張 洪明 and 浅田 邦博,
    "An optimal layout method based on compatible pair search algorithm ,"
    第6回回路とシステム 軽井沢ワークショップ, pp.61-65, Apr. 1993,
  • 池田 誠 and 浅田 邦博,
    "High Speed Data Transmission Method by Reduced Swing Signal for VLSI Bus Architecture,"
    電子情報通信学会 技術研究報告, ED93-5D, ICD93-49 pp.39-45, Jun. 1993,
  • 藤島 実 and 浅田 邦博,
    (in Japanese) "短チャネル低電源電圧CMOS回路における負荷容量の電気的評価法,"
    電子情報通信学会技術研究報告, Vol.93, No.111, pp.1-7, Jun. 1993,
  • 秋田 純一 and 浅田 邦博,
    "A Method of Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability,"
    電子情報通信学会 VLSI設計技術研究会, ED-93-83, Sep. 1993,
  • 池野 理門 and 浅田 邦博,
    "High-Speed Method for Device Simulations by Area Division,"
    第59回応用物理学会学術講演会, 28pーz7ー3、pp720, Sep. 1993,
  • 張 洪明 and 浅田 邦博,
    "A Layout Method for Logic System Designed by Parthenon,"
    1993年電子情報通信学会 秋季全国大会, A-68, pp.1-68, Sep. 1993,
  • 岩崎 靖和 and 浅田 邦博,
    "Numerical Analysis of Power Devices with Axially Symmetric Structure,"
    第54回応用物理学会 学術講演会, 28p-ZT-8, pp.722, Sep. 1993,
  • 池田 誠 and 浅田 邦博,
    "A Design of Control Circuits for Reduced Swing Signal Data Transmission Method,"
    1993年電子情報通信学会 秋季全国大会, C-441, pp.5-151, Sep. 1993,
  • K. Asada, K. Ohkura, and K. R. Cho,
    "Design of Self-Timed Data Path for a Fully Asynchronus Microprocessor,"
    SASIMI '92, pp.HLII-1, Apr. 1992,
  • M. Fujishima, M. Ikeda, K. Asada, Y. Omura, and K. Izumi,
    "Analytical Modeling of Dynamic Performance of Deep Sub-micron SOI/SIMOX Based on Current-Dwlay Product,"
    IEICE TRANS. ELECTRON.,, Vol.E75-C, No.12, Dec. 1992,
  • M. Fujishima, M. Ikeda, K. Asada, Y. Omura, and Y. Izumi,
    "Analytical Modeling of Dynamic Performance of Deep Submicron SOI/SIMOX Based on Current-Delay Product,"
    IEICE Trans. on Electronics, Vol. E75-C, No.12, Dec. 1992,
  • M. Fujishima, M. Yamashita, M. Ikeda, K. Asada, Y. Omura, K. Izumi, T. Sakai, and T. Sugano,
    "1GHz 50 μW 1/2 Frequency Divider Fabricated on Ultra-thin SIMOX Substrate,"
    IEEE 1992 Symposium on VLSI Circuit Digest of Technical Papers, 5-4, pp.46-47, Jun. 1992,
  • M. Fujishima, K. Asada, T. Sasaki, M. Yamashita, Y. Omura, M. Ikeda, K. Izumi, and T. Sugano,
    "1 GHz 50μ 11/8 Frequency Divider Fabricated on Ultra-thin SIMOX Substrate,"
    IEEE 1992 Symposium on VLSI Circuit, Digest of Technical Papers,5-4, pp.46-47, Jun. 1992,
  • H. Zhang and K. Asada,
    "A General and Efficient Mask Pattern Generator For Non-Series-Parallel CMOS Transistor Network,"
    WG10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design (France), pp.132-138, Mar. 1992,
  • 張 洪明 and 浅田 邦博,
    (in Japanese) "非直並列CMOS回路のレイアウト最適化手法,"
    1992年電子情報通信学会 秋季全国大会, A-61, Sep. 1992,
  • 趙 慶録, 大蔵 一真, and 浅田 邦博,
    (in Japanese) "非同期マイクロプロセッサの制御回路,"
    FTC研究会, Vol.FTC-26,No.1, 1992,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    "Evaluation of Dynamic Load Capacitance of CMOS Circuits,"
    第39回応用物理学関係連合講演会, 30p-ZM-13,pp.726, 1992,
  • 趙 慶録, 大蔵 一真, and 浅田 邦博,
    (in Japanese) "パイプライン構造をもつ非同期プロセッサの制御,"
    1992年電子情報通信学会春期全国大会, pp.A-97, 1992,
  • 大蔵 一真, 趙 慶録, and 浅田 邦博,
    (in Japanese) "2線式論理を用いたデータパスの設計,"
    1992年電子情報通信学会春期全国大会, pp.A-98, 1992,
  • 西山 隆裕, 藤島 実, and 浅田 邦博,
    (in Japanese) "境界要素法による3次元容量解析式の評価,"
    1992年電子情報通信学会春期全国大会, C-523,pp.5-144, 1992,
  • 張 洪明 and 浅田 邦博,
    "Layout Design with Two Dimension MOSFET Cells,"
    電子情報通信学会論文誌, Vol.J75-A,No.5,pp.960-962, 1992,
  • 藤島 実, 山下 雅樹, 池田 誠, 浅田 邦博, 菅野 卓雄, 大村 泰久, 泉 勝俊, and 酒井 徹志,
    "0.1-μm Low-Power Frequency-Divider Fabricated on Ultra-thin SIMOX Substrate,"
    電子情報通信学会招待論文, ED92-61,ICD92-46,pp.31-38, 1992,
  • 張 洪明 and 浅田 邦博,
    "An optimal layout method for non-series-parallel CMOS network,"
    1992年電子情報通信学会秋季全国大会, A-61,pp.1-61, 1992,
  • 藤島 実 and 浅田 邦博,
    "Drain-Current Modeling for Deep-Submicron MOSFETs,"
    第53回応用物理学会学術講演会, 17a-SE-9,pp.610, 1992,
  • 池田 誠 and 浅田 邦博,
    "Optimum Signal Swing for Reduced Voltage Bus Lines,"
    1992年電子情報通信学会秋季全国大会, C-429,pp.5-109, 1992,
  • 浅田 邦博, 鈴木 真一, 戴 志堅, 趙 慶録, and 藤島 実,
    (in Japanese) "MOSES MOS集積回路モジュール設計システム,"
    東京大学出版会, 1991,
  • T. Ohmameuda, H. Miki, K. Asada, T. Sugano, and Y. Ohji,
    "Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO2 Films,"
    Japanese Journal of Applied Physics, Vol.30,No.12A,pp.L1993-L1995, Dec. 1991,
  • Y. Tajima, K. Asada, and T. Sugano,
    "1/5 Power Law in PN-Junction Failure Mechanism Cased by Electrical-Over-Stress,"
    IEICE Transactions, Vol.E75-C,No.2,pp.207-215, Feb. 1991,
  • H. Miki, T. Ohmameuda, M. Kumon, K. Asada, and T. Sugano,
    "Subfemtojoule Deep Submicrometer-Gate CMOS Built In Ultra-Thin Si Film on SIMOX Substrates,"
    IEEE Transactions Electron Devices, Vol.38,No.2,pp.373-377, Feb. 1991,
  • M. Fujishima, K. Asada, and T. Sugano,
    "Evaluation of Delay-Time Degradation of Low-Voltage BiCMOS Based on a Novel Analytical Delay-Time Modeling,"
    IEEE Journal Solid-State Circuits, Vol.26,No.1,pp.25-31, Jan. 1991,
  • K. R. Cho and K. Asada,
    "VLSI Oriented Design Method of Asynchronous Sequential Circuits Based on One-Hot Code and Two-Transistor and Logic,"
    ISCAS '91, pp.1793-1796, Jun. 1991,
  • K. R. Cho, M. Ikeda, and K. Asada,
    "VLSI-Oriented Asynchronous Controller Synthesis Based on a Flip-Flop Cell Array Structure,"
    Euro ASIC '91, pp.117-122, May. 1991,
  • 大蔵 一真, 趙 慶録, and 浅田 邦博,
    (in Japanese) "非同期マイクロプロセッサの演算ブロック設計,"
    電子情報通信学会技術報告, Vol.VLD91,No.354,pp.57-63, 1991,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "回路トポロジーの多段分解による面積最小回路の一合成手法,"
    電子情報通信学会論文誌, J74-A, 1991,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "One-hot Code状態割当と2-AND論理を用いたVLSI向き非同期回路の合成,"
    電子情報通信学会論文誌, J74-A巻,2号,pp.218-226, 1991,
  • 菅野 卓雄, 浅田 邦博, and 大阪間 止,
    (in Japanese) "DRAMセル用MOSトランジスタの寸法限界,"
    電子情報通信学会サブハーフミクロンULSI技術, 1991,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "大規模論理回路の最適化設計に関する一検討,"
    1991年電子情報通信学会春期全国大会, 1991,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "CMOS非同期式回路のハードウェア量の解析的評価,"
    1991年電子情報通信学会春期全国大会, A107,pp.107, 1991,
  • 張 洪明 and 浅田 邦博,
    (in Japanese) "空間分割による不定形状配線法,"
    1991年電子情報通信学会春期全国大会, A-104,A巻,pp.104, 1991,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "ツリー状に接続された論理回路におけるMOSFETのゲート幅の解析的最適化,"
    1991年電子情報通信学会春期全国大会, C-586,pp.5-177, 1991,
  • 大豆生田 利章, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "シリコン酸化膜中の正孔捕獲中心密度に関する熱力学的検討(Ⅱ),"
    1991年(平成3年)春期第38回応用物理学関係連合講演会, 30a-SY8/Ⅱ,pp.705, 1991,
  • 田島 豊, 土屋, 村上 浩一, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "過電圧サージによるPN接合の破壊メカニズム,"
    応用物理学関係連合講演会, 29a,SX27,pp.653, 1991,
  • 大豆生田 利章, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "シリコン酸化膜中の正孔捕獲中心密度に関する熱力学的検討(Ⅱ),"
    応用物理学関係連合講演会, 30a,SY8/Ⅱ,pp.705, 1991,
  • 趙 慶録, 田中 範明, and 浅田 邦博,
    (in Japanese) "最小トランジスタ指標にもとづくCMOS複合ゲート型非同期順序回路の動作記述からの合成,"
    電子情報通信学会論文誌, J74-B-I巻,3号,pp.489-498, 1991,
  • 張 洪明 and 浅田 邦博,
    (in Japanese) "空間分割による不定形状における配線手法,"
    CAS,VLD,DSP共同研究会, VLD91-25,pp.7-15, 1991,
  • 張 洪明 and 浅田 邦博,
    (in Japanese) "配線容易化のための配置設計手法,"
    1991年電子情報通信学会 秋季全国大会, A-49, 1991,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "VLSIにおけるブロック相互間制御回路の動作解析,"
    1991年電子情報通信学会秋季全国大会, pp.A-45, 1991,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "新しいバイナリーキャリールックアヘッドを用いた高速加算器およびカウンタの構成,"
    1991年電子情報通信学会秋季全国大会, C-391,pp.5-105, 1991,
  • 浅田 邦博, 藤島 実, 菅野 卓雄, 大村, and 泉,
    (in Japanese) "極薄膜超微細化MOSFET/SOIのモデル化と動作解析,"
    東京大学工学部総合試験所年報, 50巻,pp.73-77, 1991,
  • 立石 哲夫 and 浅田 邦博,
    "A Statistical Modeling of Charge Redistribution A-D Converters for Yield Optimum Design,"
    電子情報通信学会論文誌, A Vol.J73-A, No.8, pp.1359-1367, 1990,
  • T. Shinohara, K. Asada, and T. Sugano,
    "Performance Analysis of Polycrystalline Silicon Thin-Film Transistor Based on a Model of Depletion Layer Width Modelation at Gain Boundaries,"
    Electronics and Communications in Japan, Part 2, Vol.73,No.7,pp.106-116, Jul. 1990,
  • M. Fujishima, K. Asada, and T. Sugano,
    "Appraisal of BiCMOS from Circuit Voltage and Delay Time,"
    1990 Symposium on VLSI Circuits, Vol.9-5, 1990,
  • Z. J. Dai and K. Asada,
    "Topology Decomposition for Area-minimum Multistage Complex Gates Synthesis,"
    IEEE Prof. Custom Integrated Circuits Conf., pp.14.2.1-14.2.5, 1990,
  • K. Asada and J. Mayor,
    "MOSYN: a MOS circuit synthesis program employing 3-way decomposition and reduction based on seven-valued logic,"
    IEE Proceedings, Vol.137, Pt.E, No.6, pp.451-461, Nov. 1990,
  • 浅田 邦博, 趙 慶録, and 戴 志堅,
    (in Japanese) "VLSI向き論理合成および回路最適化手法の動向,"
    電子情報通信学会回路とシステムワークショップ, A-69, 1990,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "低電圧BiCMOS回路における遅延時間の比較,"
    電子情報通信学会(秋季大会), SC-10-7,pp.5-309〜5-310, 1990,
  • 戴 志堅, 鈴木 真一, and 浅田 邦博,
    (in Japanese) "MOS回路の面積見積り式,"
    電子情報通信学会(秋季大会), A-69, 1990,
  • 張 洪明 and 浅田 邦博,
    (in Japanese) "空間分割による配線法の提案,"
    電子情報通信学会(秋季大会), A-74,pp.74, 1990,
  • 大豆生田 利章, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "シリコン酸化膜の正孔捕獲中心に関する熱力学的検討,"
    シリコン・デバイス研究会,集積回路研究会共催, SDM90-129,pp.69-74, 1990,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "新しい遅延-面積見積り式を用いたMOS回路モジュールの最適設計,"
    電子情報通信学会技術研究報告, VLD90-73,pp.49-56, 1990,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "解析手法による低電圧BiCMOS回路の遅延時間劣化の見積り,"
    シリコン・デバイス研究会,集積回路研究会共催, SDM90-59,ICD90-74,pp.7-14, 1990,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "CMOS非同期式順序回路のハードウェア量の解析的評価,"
    1990年電子情報通信学会春期全国大会, A-107,pp.1-107, 1990,
  • 立石 哲夫 and 浅田 邦博,
    (in Japanese) "A/D,D/A変換器用2進重みキャパシタアレイの統計的誤差解析,"
    1990年電子情報通信学会春期全国大会, A-44, 1990,
  • 三木 浩史, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "超ドライ低温酸素アニールによるSio2中の正孔トラップの低減,"
    1990年(平成2年)春期第37回応用物理学関係連合講演会, 29p-ZC-2, 1990,
  • 中畔 邦雄 and 浅田 邦博,
    (in Japanese) "カスコード電圧スイッチ論理を用いたセルフチェッキングLSIシステム構成法,"
    1990年電子情報通信学会春期全国大会, D-247,pp.6-249, 1990,
  • 三木 浩史, 大豆生田 利章, 久門 正和, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "低消費電力SOI/SIMOX CMOSリングオシレータ,"
    1990年(平成2年)春期第37回応用物理学関係連合講演会, 30p-ZD-13, 1990,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "MOSの高精度線形近似法とCMOS/BiCMOS回路の遅延時間への応用,"
    1990年(平成2年)春期第37回応用物理学関係連合講演会, O巻,29p-ZD-14, 1990,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "最大許容遅延時間割付による多段複合MOS回路のトランジスタ寸法の2段階最適化手法,"
    電子情報通信学会論文誌, J73-A巻,pp.526-536, 1990,
  • 菅野 卓雄, 浅田 邦博, and 大阪間 止,
    (in Japanese) "DRAMセル用MOSトランジスタの寸法限界,"
    電子情報通信学会「サブハーフミクロンULSIテクノロジー」, 1990,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "1ビット変化の状態割当てを用いた非同期式順序回路の合成,"
    電子情報通信学会(秋季大会), SA-3-6,pp.1-233, 1990,
  • K. R. Cho and K. Asada,
    "Comparison of asynchronous sequential machines realized by CMOS random logic circuit and PLAs with transition detectors,"
    The Proceeding of ICSICT'89 Bejing China, Vol.2,pp.533-534, Jun. 1989,
  • H. Miki, T. Ohmameuda, M. Kumon, K. Asada, and T. Sugano,
    "Fabrication and Characterization of a Quarter micron Gate CMOS using Ultra-thin Si Film (30nm) on SIMOX Substrate,"
    International Electron Devices Meeting,1989, pp.906-911, Jun. 1989,
  • H. Miki, K. Asada, and T. Sugano,
    "Effects of Ultra Dry Ar Annealing on the annihilation and creation of electron/hole trap in Sio2 grown on Si substrates,"
    Passivation of Metal and Semiconductors, pp.395-400, Jun. 1989,
  • H. Miki, K. Asada, and T. Sugano,
    "Effect of the ultra-dry post oxidation anneal on the density of carrier traps in thin SiO2 films,"
    Sixth International Symposium on Passivity, 1989,
  • F. Hatori, K. Asada, and T. Sugano,
    "Cascade Model for Reduction of Field-Effect Mobility of Electrons in Lightly Deped Channel of Submicron Gate Si Thin-Film Field-Effect Transisters,"
    Japanese Journal of Applied Physics, Vol.28,No.8,pp.1348-1353, Aug. 1989,
  • S. Tanimoto, T. Mihara, K. Asada, and T. Sugano,
    "A possible mechanism of electron injection for the threshold voltage shift of metal-oxide-semicondoctor field-effect transistors at low voltage ,"
    Japanese Journal of Applied Physics, Vol.65, No.10, 1989,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "MOS回路の多段分解による回路の最適自動合成,"
    電子情報通信学会・VLSI設計技術研究会, VLD89-71,pp.9-16, 1989,
  • 篠原 俊朗, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "粒界空乏層変調モデルによる多結晶シリコン薄膜トランジスタの動作シミュレーション,"
    電子情報通信学会論文誌, C-Ⅱ巻,J72号,pp.919-926, 1989,
  • 三木 浩史, 大豆生田 利章, 久門 正和, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "SIMOX基板を用いた極薄膜SOI-MOSFET'sの特性解析,"
    電子情報通信学会・シリコン材料・デバイス研究会, SDM巻,89-125,pp.29-34, 1989,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "2段パスロジックによる非同期式順序回路の合成,"
    電子情報通信学会・VLSI設計技術研究会, 89巻,339号,VLD89-83,pp.1-8, 1989,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "複合構造を用いた相補型BiCMOS回路,"
    電子情報通信学会論文誌, J72巻,12号,pp.1171-1174, 1989,
  • 趙 慶録, 田中 範明, and 浅田 邦博,
    (in Japanese) "MOS複合ゲートによる非同期順序回路の合成,"
    電子情報通信学会・回路とシステム研究会, CAS88-118,pp.85-92, 1989,
  • 趙 慶録, 田中 範明, 久木元 裕治, and 浅田 邦博,
    (in Japanese) "速度独立性を持つ非同期PLA順序回路の自動合成手法,"
    電子情報通信学会・VLSI設計技術研究会, VLD88-112,pp.9-16, 1989,
  • 田中 範明 and 浅田 邦博,
    (in Japanese) "非同期順序回路の機能記述の一考察,"
    電子情報通信学会春期全国大会, A-245,pp.1-248, 1989,
  • 木下 聡, 戴 志堅, and 浅田 邦博,
    (in Japanese) "MOS複合論理回路の多段分解に関する提案,"
    電子情報通信学会春期全国大会, C-271,pp.5-222, 1989,
  • 趙 慶録, 久木元 裕治, and 浅田 邦博,
    (in Japanese) "非同期式順序回路のPLA化設計,"
    電子情報通信学会春期全国大会, A-234,pp.1-247, 1989,
  • 阿部 憲幸 and 浅田 邦博,
    (in Japanese) "高級言語機能記述入力による多層クロック分配形論理LSIの自動構成システム,"
    電子情報通信学会春期全国大会, A-234,pp.1-237, 1989,
  • 藤島 実, 八杉 昌宏, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "融合デバイス構造を用いた新BiCMOS回路の提案,"
    電子情報通信学会春期全国大会, C-274, 1989,
  • 曽根 裕, 鈴木 真一, and 浅田 邦博,
    (in Japanese) "3次元迷路法によるCMOS中規模セル合成手法,"
    電子情報通信学会春期全国大会, SA-7-4,pp.398-399, 1989,
  • 三木 浩史, 浅田 邦博, 菅野 卓雄, and 大村 泰久,
    (in Japanese) "SOI基板を用いたDeep SubmicronゲートMOSFETにおける電界効果移動度の低下現象(Ⅱ),"
    1989年(平成元年)春期第36回応用物理学関係連合講演会, ZH 8/Ⅱ, 1989,
  • 羽鳥 文敏, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "SOI基板を用いたDeep SubmicronゲートMOSFETにおける電界効果移動度の低減現象(Ⅰ),"
    1989年(平成元年)春期第36回応用物理学関係連合講演会, ZH 7/Ⅱ, 1989,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "融合構造を用いた高性能コンプリメンタリBiCMOS回路,"
    電子情報通信学会・シリコン材料・デバイス研究会, 89巻,139号,SDM89-58,pp.59-63, 1989,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "融合構造を用いた高性能コンプリメンタリBiCMOS回路,"
    電子情報通信学会・集積回路研究会, ICD89-81,pp.59-64, 1989,
  • 趙 慶録 and 浅田 邦博,
    (in Japanese) "線形コードを用いたパスロジック非同式順序回路,"
    1989年電子情報通信学会秋季全国大会, A-91,A巻,pp.1-94, 1989,
  • 藤島 実, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "複合構造を用いたBiCMOS回路(2)-スタティック回路とダイナミック回路-,"
    1989年電子情報通信秋季全国大会, SC7-2,5号,pp.199-200, 1989,
  • 菅野 卓雄, 浅田 邦博, and 福岡 崇之,
    (in Japanese) "光励起電子放出によるSio2中の深い捕獲中心準位の測定,"
    東京大学工学部総合試験所年報, 48巻,pp.103-109, 1989,
  • 菅野 卓雄, 浅田 邦博, 羽鳥 文敏, and 三木 浩史,
    (in Japanese) "SIMOX MOSFETにおける短チャネル効果,"
    東京大学工学部総合試験所年報, 48巻,pp.95-102, 1989,
  • H. Miki, M. Noguchi, K. Yokogawa, B. W. Kim, K. Asada, and T. Sugano,
    "Electron and Hole Traps in SiO2 Films Thermally Grown on Si Substrates in Ultra-Dry Oxygen,"
    IEEE Transaction on Electron Devices, Vol.35,No.12,pp.2245-2252, Dec. 1988,
  • W. H. Lee, T. Osakama, K. Asada, and T. Sugano,
    "Design Methodology and Size Limitations of Submicrometer MOSFET's for DRAM Application,"
    IEEE Transactions on Electron Devices, Vol.35,No.11,pp.1876-1884, Nov. 1988,
  • 三木 浩史, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "超ドライ酸化膜中の正孔トラップ密度,"
    1988年(昭和63年)秋季第49回応用物理学会学術講演会, 6aN 11/Ⅱ, 1988,
  • 篠原 俊朗, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "多結晶シリコン粒界バリアの変調に基づくキャリア輸送モデリングとFET動作解析への応用,"
    1988年(昭和63年)春期第35回応用物理学連合講演会, 30p-ZE4, 1988,
  • 丸井 智敬, 戴 志堅, and 浅田 邦博,
    (in Japanese) "MOS回路トランジスタサイジングの一手法,"
    昭和63年電子情報通信学会春期全国大会, pp.2-218, 1988,
  • 浅田 邦博 and 他,
    (in Japanese) "プロセス・デバイス・シミュレーション技術,"
    産業図書, 1988,
  • 篠原 俊朗, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "粒界空乏層変調モデルによるポリSi-TFTシミュレーション,"
    電子情報通信学会・シリコン材料・デバイス研究会, SDM88,pp.27-34, 1988,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "多段複合ゲート回路の遅延時間最適化方法,"
    電子情報通信学会・シリコン材料・デバイス研究会, SDM88-79,pp.15-22, 1988,
  • 藤島 実 and 浅田 邦博,
    (in Japanese) "モジュールジェネレーション用トランジスタ配置プランナ,"
    電子情報通信学会秋季全国大会, C-102,pp.C-2-83, 1988,
  • 戴 志堅, 丸井 智敬, and 浅田 邦博,
    (in Japanese) "多段ゲートのタイミング最適割付方法,"
    電子情報通信学会秋季全国大会, C-106,pp.C-2-87, 1988,
  • 趙 慶録, 山下 雅樹, and 浅田 邦博,
    (in Japanese) "MOS複合ゲートによる非同期式順序回路の最適状態割当て,"
    電子情報通信学会秋季全国大会, A-81, 1988,
  • 曽根 裕, 鈴木 真一, and 浅田 邦博,
    (in Japanese) "ランダム配置セルの3次元配線手法,"
    電子情報通信学会秋季全国大会, A-84,pp.A-1-85, 1988,
  • K. Asada and J. Mavor,
    "A MOS Leaf-Cell Generation System from Booleam Expressims,"
    Proceeding of the IEEE 1987 Custom Integrated Circuit Conference, pp.25-28, 1987,
  • 浅田 邦博 and Jメイバー,
    (in Japanese) "論理LSI用モジュール回路・レイアウトの自動合成,"
    電子情報通信学会研究会, VLD87-95,pp.33-37, 1987,
  • 金 輔祐, 三木 浩史, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "正孔注入によるSiO2評価の問題点,"
    1987年(昭和62年)秋季第48回応用物理学会学術講演会, 19pL-11/Ⅱ, 1987,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "MOS回路のロジックパスに基づくトランジスタサイジング,"
    昭和62年電子情報通信学会半導体・材料部門全国大会, No.100, 1987,
  • 戴 志堅 and 浅田 邦博,
    (in Japanese) "教育用会話型LSIレイアウト設計システムの開発,"
    東京大学工学部紀要(A), 25巻,34-35, 1987,
  • 戴 志堅, 杉田 夏樹, 梶田 公司, and 浅田 邦博,
    (in Japanese) "会話型レイアウト設計システム用任意精度回路シミュレータの開発,"
    昭和62年電子情報通信学会創立70執念記念総合全国大会講演論文集, No.323, 1987,
  • 谷本 智, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "低電圧ゲート酸化膜電子注入現象に関するフォノン吸収モデルの実験的検証,"
    1987年(昭和62年)春期第34回応用物理学関係連合講演会, 29p-O-2, 1987,
  • 梶田 公司, 白畑 厚志, 高橋 徹, and 浅田 邦博,
    (in Japanese) "ライブラリを用いないカスタムLSI設計法,"
    昭和62年電子情報通信学会創立70周年記念総合全国大会講演論文集, No.338, 1987,
  • 李 文豪, クライソン・トロンナムチャイ, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "DRAM用サブミクロンMOSFETの設計限界,"
    電子情報通信学会集積回路研究会, ICD-87, 1987,
  • 浅田 邦博,
    (in Japanese) "パソコンを用いた集積回路教育の実施例(Ⅰ),"
    昭和62年電気学会全国講演論文集, S.6-4, 1987,
  • 浅田 邦博,
    (in Japanese) "カスタム集積回路コンファレンス(CICC)から,"
    第38回設計自動化研究会, 1987,
  • 浅田 邦博,
    (in Japanese) "画像用LSIの設計技術,"
    昭和62年テレビジョン学会全国大会, S3-5,pp.477-480, 1987,
  • 野沢 成禎, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "Si薄膜の評価技術(2),"
    東京大学工学部総合試験所年報, 46巻,pp.83-87, 1987,
  • K. Asada and J. Mavor,
    "Area Optimized MOS Circuit Generation Using the Circuit Synthesis Program MOSYN-2,"
    12th European Solid-State Circuit Conference, Delft,Sept.16-18,pp.21-24, Sep. 1986,
  • E. M. Murray, T. Sugano, and K. Asada,
    "The Characterization of the Variability of Silicon Wafers by Leakage Current Measurements,"
    Japanese Journal of Applied Physics, Vol.25,No.2,pp.L99-L101, Feb. 1986,
  • K. Throngnumchai, K. Asada, and T. Sugano,
    "Modeling of 0.1 μm MOSFET on SOI Structure Using Monte Carlo Simulation Technique,"
    IEEE Transaction Electron Devices, Vol.ED-33,No.7,pp.1005-1011, Jul. 1986,
  • クライソン・トロンアンムチャイ, 永井 亮, 星野 洋, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "埋め込みP+型パンチスルーMOSデバイスの特性,"
    1986年春期第33回応用物理学関係連合講演会, 4p-Q-15, 1986,
  • 菅野 卓雄 and 浅田 邦博,
    (in Japanese) "SiO2中の捕獲中心の測定,"
    東京大学工学部総合試験所年報, 45巻,pp.83-88, 1986,
  • 野沢 成禎, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "Si薄膜の評価技術,"
    東京大学工学部総合試験所年報, 45巻,pp.77-81, 1986,
  • T. Sugano, K. Asada, T. Sakurai, and N. Haneji,
    "Model for Traps with Broad Energy Level and Determination of Trap-Density vs Capture Cross-Section,"
    Proc. of 1984 Seoul Int. Sympo. on Phys. of Semicon. and Its appli., pp.174-187, 1985,
  • N. Haneji, F. Arai, K. Asada, and T. Sugano,
    "Anodic Oxidation of Si in Oxygen/Chlorine Plasma,"
    IEEE Transaction on Electron Devices, Vol.Ed-32N,No.2,pp.100-105, 1985,
  • 野沢 成禎, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "高抵抗率エピ層のDLTSによる評価,"
    1985年(昭和60年)秋季第46回応用物理学会学術講演会, 2p-Y-8, 1985,
  • 浅田 邦博 and 他,
    (in Japanese) "VLSIの設計Ⅰ,"
    岩波, 1985,
  • 浅田 邦博 and 他,
    (in Japanese) "VLSIの設計II,"
    岩波, 1985,
  • クライソン・トロンナムチャイ, 三原 輝儀, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "モンテカルロ法によるキャリアエネルギ分布の計算,"
    1985年春期第32回応用物理学関係連合講演会, 1a-E-6, 1985,
  • 浅田 邦博, 三原 輝儀, クライソン・トロンナムチャイ, and 菅野 卓雄,
    (in Japanese) "短チャンネルMOSFETにおけるホットキャリア統計,"
    1985年春期第32回応用物理学関係連合講演会, 30p-V-6, 1985,
  • 浅田 邦博 and 菅野 卓雄,
    (in Japanese) "MOS LSI セル最適設計法に関する一考察,"
    電子通信学会半導体トランジスタ研究会, SSD84-76, 1984,
  • 浅田 邦博, クライソン・トロンナムチャイ, 三原 輝儀, and 菅野 卓雄,
    (in Japanese) "電位制御型MOSトランジスタの特性の計算機解析,"
    1984年秋季第45回応用物理学会学術講演会, 14p-Q-5, 1984,
  • 羽路 伸夫, 新井 夫差子, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "O2/Cl2プラズマによるSiの陽極酸化,"
    1984年秋季第45回応用物理学会学術講演会, 14p-B-14, 1984,
  • 石藤 智昭, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "MOSLSIセル形状最適化システムのための会話形スティック線図エディタ,"
    昭和59年電子通信学会総合全国大会, No.402, 1984,
  • 浅田 邦博, 星野 洋, and 菅野 卓雄,
    (in Japanese) "東京大学におけるLSI設計試作教育経験,"
    昭和59年電気学会全国大会, S5-5, 1984,
  • 浅田 邦博 and 他,
    (in Japanese) "VLSIシステム設計 サブロー・ムロガ著,"
    ワイリージャパン, 1984,
  • 吉田 育生, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "縮小CMOS,nMOSインバータのシミュレーションによる性能評価,"
    電子通信学会論文誌, J66-C巻,12号,p.1019-1026, 1983,
  • 羽路 伸夫, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "ディジタル化電子なだれ注入装置の試作とSiO2中の捕獲中心面密度分布の新しい算出法,"
    電子通信学会論文誌, J66-C巻,12号,p.1067-1071, 1983,
  • 浅田 邦博,
    (in Japanese) "DLTS測定法,"
    日本電子工業振興会シリコン新デバイスに関する調査研究報告書Ⅱ, 58-M-205,p.22, 1983,
  • 浅田 邦博,
    (in Japanese) "集積回路研究教育状況,"
    日本電子工業振興会シリコン新デバイスに関する調査研究報告書Ⅱ, 58-M-205,p.159, 1983,
  • 羽路 伸夫, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "アバランシェ・インジェクション法のディジタル化,"
    1983年(昭和58年)春期第30回応用物理学関係連合講演会, 7p-P-2, 1983,
  • 吉田 育生, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "縮小CMOS,nMOSインバータの性能評価,"
    電子通信学会半導体・トランジスタ研究会, SSD83-27, 1983,
  • 羽路 伸夫, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "捕獲断面が分布したモデルでのSiO2中のトラップ面密度の算出法,"
    1983年(昭和58年)秋季第44回応用物理学会学術講演会, 29pO1, 1983,
  • クライソン・トロンナムチャイ, 物井 誠, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "低不純物密度SOI構造MOSFETのニアシュレッショルドにおける簡易モデル,"
    電子通信学会半導体・材料部門全国大会, No.71, 1983,
  • 浅田 邦博, 森田 真司, and 菅野 卓雄,
    (in Japanese) "区間的線形等価回路に基づくLSIセル形状の最適化手法,"
    電子通信学会半導体・材料部門全国大会, No.152, 1983,
  • 浅田 邦博, 森田 真司, and 菅野 卓雄,
    (in Japanese) "MOS集積回路用セルレイアウトの最適化手法,"
    東京大学工学部総合試験所年報, 42巻,p.59, 1983,
  • 菅野 卓雄, 浅田 邦博, and 中野 義昭,
    (in Japanese) "反応性イオンエッチングプラズマ中のイオン質量分析,"
    東京大学工学部総合試験所年報, 42巻,p.81, 1983,
  • K. Asada and T. Sugano,
    "Automatic Deconvolution in DLTS Signals Analysis,"
    The Transaction of the IECE of Japan, Vol.E65,No12,pp.745-749, Dec. 1982,
  • K. Asada and T. Sugano,
    "Simple microcomputerbased apparatus for combined DLTS-C-V measurements,"
    Review of Scientific Instruments, Vol.53,No.7,pp.1001-1006, Jul. 1982,
  • Y. Nakano, K. Asada, and T. Sugano,
    "Dwtection of Ions in Reactive Etching Plasma Using QMS Without the Ionizer,"
    第6回イオン源とイオンを基礎とした応用技術, p.241, Jun. 1982,
  • グェン ニユット, 浅田 邦博, 大山, 斉藤, and 猪瀬,
    (in Japanese) "環状結合網を用いた分散型データフロー計算機の一方式,"
    電気通信学会論文誌, Vol.J65-D,No.12,p.1528, Dec. 1982,
  • 中野 義昭, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "一部改造した四重極質量分析計によるRIEプラズマ中のイオン質量分析,"
    電子通信学会半導体・トランジスタ研究会, SSD82-47, 1982,
  • 飯島 晋平, 松本 比呂志, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "反応性イオンエッチングにおけるプラズマの発光分析とSiおよびSiO2のエッチング速度との関連,"
    電子通信学会半導体・トランジスタ研究会, SSD82-48, 1982,
  • 菅野 卓雄, 浅田 邦博, and 葉 清発,
    (in Japanese) "ビーム・リソグラフィにより導入されるSiO2中の中性トラップ,"
    東京大学工学部総合試験所年報, Vol.41,p.111, 1982,
  • 菅野 卓雄, 浅田 邦博, and 松本 比呂志,
    (in Japanese) "SiF4ガスを用いたリアクティブ・イオン・エッチング,"
    東京大学工学部総合試験所年報, Vol.41,p.105, 1982,
  • 浅田 邦博 and 菅野 卓雄,
    (in Japanese) "DLTS信号の自動処理,"
    1981年(昭和56年)秋季第42回応用物理学会学術講演会, 9p-C-1, 1981,
  • 松本 比呂志, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "スタンフォード大学プロセスシミュレータ SUPREMについて,"
    電気学会研究会資料:電子デバイス,システム,制御合同研究会, EDD 81,p.1, 1981,
  • 浅田 邦博 and 菅野 卓雄,
    (in Japanese) "計算機を用いたDLTS測定の自動化,"
    1981年(昭和56年)春期第28回応用物理学関係連合講演会, 30a-L-8, 1981,
  • 浅田 邦博 and 菅野 卓雄,
    (in Japanese) "ディジタル化した高速DLTS測定装置の試作,"
    応用物理学会応用電子物性分科会研究報告, 1981,
  • 菅野 卓雄 and 浅田 邦博,
    (in Japanese) "ディジタル化自動DLTS測定装置の試作,"
    東京大学工学部総合試験所年報, 40巻,p.83, 1981,
  • 菅野 卓雄 and 浅田 邦博,
    "Introduction to VLSI Systems,"
    培風館, 1981,
  • 浅田 邦博 and 菅野 卓雄,
    (in Japanese) "ディジタル化自動DLTS測定装置の試作,"
    電子通信学会半導体トランジスタ研究会, SSD81-21,p.1, 1981,
  • 葉 清発, 桜井 貴康, 浅田 邦博, and 菅野 卓雄,
    (in Japanese) "SiO2中の中性トラップの測定,"
    電子通信学会半導体トランジスタ研究会, SSD81-48,p.7-14, 1981,
  • 菅野 卓雄 and 浅田 邦博,
    (in Japanese) "LSIの進歩と教育の役割,"
    昭和55年電気四学会連合大会, No.17-6,pp.75-78, 1980,
  • 大山, 浅田 邦博, 斉藤 忠夫, and 猪瀬 博,
    (in Japanese) "分散型データフロー計算機のプログラムモデルを用いた性能評価,"
    電子通信学会電子計算機研究会, EC80-14, 1980,
  • 浅田 邦博,
    (in Japanese) "計算機複合体における故障診断修復方式に関する研究,"
    , 1980,
  • 浅田 邦博, 蓮池 和夫, 熊崎 基澄, 斉藤 忠夫, and 猪瀬 博,
    (in Japanese) "マイクロプロセッサを含む知能末端の遠隔診断修復の一方式,"
    電気学会論文誌, Vol.54-C, No.28, 1979,
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