Clock-Data Recovery Circuit

Clock-Data Recovery Circuit is an important block in serial communication systems. For developing serial communication systems which perform intermittent communication, such as sensor networks, current CDR circuits have problems with the amount of power consumption because they consume a certain amount of power even in their stand-by state or in their warming-up state. That is why we propose this CDR circuit which does not consume active power in its stand-by state and gets ready to communicate just after a 4-bit preamble signal. By using this circuit, it is going to be possible to reduce power consumption of serial communication systems for IoT applications.