研究員のChenとD3のDevlinがCOOL Chips XVで発表

5/18/2012

  研究員のChenとD3のDevlinがIEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XV)で発表しました。

表題「Dual-Stage Hardware Architecture of On-Line Clustering with High-Throughput Parallel Divider for Low-Power Signal Processing」(Chen)

表題「Gate-level Process Variation Offset Technique by using Dual Voltage Supplies to Achieve Near-threshold Energy Efficient Operation」(Devlin)