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Name :
- Tetsuya Iizuka
- Current Belongings and Title :
- Associate Professor at Systems Design Lab., School of Engineering, The University of Tokyo, Japan
- E-mail address :
- iizuka[AT]vdec.u-tokyo.ac.jp
- Lab. Webpage :
- https://www.mos.t.u-tokyo.ac.jp/iizuka/en/
- Contact Address :
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VLSI Design and Education Center, University of Tokyo
Takeda Bldg., Room 415,
2-11-16 Yayoi, Bunkyo-ku, Tokyo 113-0032, JAPAN
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- History :
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2002 March: B.S. in Electronic Engineering, University of Tokyo
2004 March: M.S. in Electronic Engineering, University of Tokyo
2004 April: Research Fellow of the Japan Society for the Promotion
of Science(until March 2007)
2007 March: Ph.D. in Electronic Engineering, University of Tokyo
[PDF]
2007 April: Start Working as an Analog/Mixed-Signal LSI Designer
(Designed Analog IP Macro for High-Speed Serial Interfaces, etc.)
2009 April: Assistant Professor with VLSI Design and Education Center,
The University of Tokyo
2011 February: Assistant Professor with Dept. of Electrical Engineering
and Information Systems, The University of Tokyo
2013 April : Visiting Scholar with Dept. of Electrical Engineering,
University of California, Los Angeles (Mentor: Prof. Asad A. Abidi)
(JSPS Postdoctoral Fellowships for Research Abroad, until March 2015)
2014 April : Associate Professor with Dept. of Electrical Engineering
and Information Systems, The University of Tokyo
2015 April: Associate Professor with VLSI Design and Education Center,
The University of Tokyo
2019 August : Visiting Scholar with Dept. of Electrical and Computer Engineering,
University of California, Los Angeles (Mentor: Prof. Asad A. Abidi)
(The University of Tokyo Global Activity Support Program for Young Researchers,
until November 2019)
2019 October: Associate Professor with Systems Design Lab.,
School of Engineering, The University of Tokyo
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- Skills :
- Operating Systems: Mac OS X, Windows, Unix and Linux operating systems
- Programming Language: C/C++, Perl, Tcl/Tk, shell scripting
- Software Development Tools: gcc, gdb, Visual Studio
- Hardware Description Language: VerilogHDL
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| VLSI Design: |
Designed digital/analog full-custom chips |
| | Analog IP Macro for High-Speed Serial Interfaces |
| | CMOS Processes: 0.35um / 0.18um / 0.13um SOI / 90nm / 65nm / 28nm FDSOI |
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| VLSI Testing: |
LSI Testers: Verigy V93000, Advantest T2000, Schlumberger ITS9000EXa |
| | EB Prober: Schlumberger IDS5000ZX/IDS10000ZX Probe System |
| | GPIB Programming |
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| EDA Tools: |
Synopsys: Design Compiler, Astro, IC-Compiler, PrimeTime-SI, |
| | HSPICE, NanoSim, HSIM, XA, VCS, TetraMAX, Hercules, Star-RCXT |
| | Cadence: Spectre, Virtuoso, Assura, QRC, NC-Verilog, Verilog-XL, Verilog-AMS |
| | Mentor: Calibre |
| | Agilent: ADS |
- Language: Japanese(native language), English(fluent)
Tetsuya Iizuka
Dept. of Electrical Engineering and Information Systems, Univ. of Tokyo
e-tet@ieee.org
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