論文・発表リスト (Published articles)



学会誌論文 (Full Paper)


Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A PLL Compiler from Specification to GDSII,''
IEICE Trans. on Fundamentals, Dec. 2017 (to be published).

Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring,''
IEICE Trans. on Electronics, Vol.E100-C, No.9 Sep. 2017.

Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Design, Analysis and Implementation of Pulse Generated by CMOS Flipped on Glass for Lower Power UWB-IR'',
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol.E100-A, No.1, pp.220-209, Jan. 2017.

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada,
``Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing'',
IEICE Trans. on Electronics, Vol.E99-C, No.10, pp.1219-1225, Oct. 2016.

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada,
``Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing'',
Journal of Electronic Testing: Theory and Application (JETTA), Vol.32, Issue 3, pp.257-271, June 2016.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Systems'',
Journal of Circuits, Systems and Computers (JSCS), vol. 25, No. 3, pp.1640017-1-1640017-16, March 2016.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A 15×15 Single Photon Avalanche Diode Sensor Featuring Breakdown Pixels Extraction Architecture for Efficient Data Readout'',
Japanese Journal of Applied Physics (JJAP), vol.55, No.4s, 04EF04, March 2016.

Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada,
``An on-chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface'',
IEICE Trans. on Electronics, Vol. E99-C, No.2, pp.257-284, Feb. 2016.

Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada,
``Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer'',
IEICE Trans. on Electronics, Vol.E98-C, No.7 July 2015.

Toru Nakura, Hiroaki Matsui, Kunihiro Asada,
``Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guideline'',
IEICE Electronics Express, Vol.12 No.3, pp.1-8, Feb. 2015.

Jinmyoung Kim, Toru Nakura, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``On-Chip Switched Decaupling Capacitors for Fast Voltage Hopping of DVS Systems'', IEICE Trans. on Electronics, Vol.E96-C, No. 4, pp. 560-567, April 2013.

Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Frequency Resolution Enhancement for Digitally-Controlled Oscillator based on a Single-Period Switching Scheme'',
IEICE Trans. on Electronics, Vol.E95-C, No.12, pp.1857-1863, Dec. 2012.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction'',
IEICE Trans. on Electronics, Vol.E95-C, No.4, pp.643-650, April 2012.

Toru Nakura, Kunihiro Asada,
``Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter'',
IEICE Trans. on Electronics, Vol.E95-C No.2, pp.297-302, March. 2012.

Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``1.0ps Resolution Time-to-Digital Converter based on Cascaded Time-Difference-Amplifier utilizing Differential Logic Delay Cells'',
IEICE Trans. on Electronics, Vol.E94-C, No.6, pp.1098-1104, 2011.

Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada,
``Cascaded Time Difference Amplifier With Differential Logic Delay Cell'',
IEICE Trans. on Electronics, Vol.E94-C, No.4, pp.654-662, April 2011.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch'',
IEICE Trans. on Electronics, Vol.E94-C, No.4, pp.511-519, 2011.

Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter'',
IEICE Trans. on Electronics, Vol.E94-C, No.4, pp.487-494, April 2011.

Devlin Benjamin Stefan, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``A Low Power and High Throughput Self Synchronous FPGA using 65nm CMOS with Throughput Optimization by Pipeline Alignment'',
IEICE Trans. on Electronics, Vol.E93-A, No.7, pp.1319-1328, Jul. 2010.

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``A 8bit Two Stage Time-to-Digital Converter using Time Difference Amplifier'',
IEICE Electronics Express, vol. 7, no.13, pp.943-948, Jul. 2010.

Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada,
``Time Difference Amplifier with Robust Gain Using Closed-Loop Control'',
IEICE Trans. on Electronics, Vol.E93-C No.3, pp.303-308, March. 2010.

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58fps 2-D Simultaneous Capture Capability'',
IEICE Trans. on Electronics, Vol.E92-C No.6, pp.798-805, June. 2009.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Autonomous di/dt Control of Power Supply for Margin Aware Operation'',
IEICE Trans. on Electronics, Vol.E89-C No.11, pp.1689-1694, Nov. 2006. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply'',
IEICE Trans. on Electronics, Vol.E89-C No.3, pp.364-369, March 2006. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs'',
IEICE Trans. on Electronics, Vol.E88-C No.8, pp.1734-1739, August 2005. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit'',
IEICE Trans. on Electronics, Vol.E88-C No.5, pp.782-787, May 2005. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Stub vs. Capacitor for Power Supply Noise Reduction'',
IEICE Trans. on Electronics, Vol.E88-C No.1, pp.125-132, Jan. 2005. [PDF File]

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara,
``A 3.6Gb/s 340-mW 16:1 Pipe-Lined Multiplexer using 0.18um SOI-CMOS Technology'',
IEEE Journal of Solid-State Circuits, Vol.35, No.5, pp.751-756, May 2000. [PDF File]

Toru Nakura, Yoshiaki Nakano,
``LAPAREX - An Automatic Parameter Extraction Program for Gain- and Index- Coupled Distributed Feedback Semiconductor Lasers, and Its Application to Observation of Changing Coupling Coefficients with Currents'',
IEICE Trans. on Electronics, Vol.E83-C No.3, pp.488-495, March 2000. [PDF File]




国際会議 (International Conference Presentations)


Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada,
``A SPAD Array Sensor based on Breakdown Pixel Extraction Architecture with Ba\ ckground Readout for Scintillation Detector,''
IEEE Sensors, Oct. 2017 (to be published).

Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Impulse Signal Generator based on Current-Mode Excitation and Transmission Line Resonator,''
IEEE New Circuit and System Conference (NEWCAS), pp.257-260, June. 2017.

Neoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada,
``Extension of Power Supply Impedance Emulation Method on ATE for Multiple Power Domain,''
IEEE European Test Symposium (ETS), Sess.P1-4, May. 2017.

Yuki Oda, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Analysis of VLSI Power Supply Network based on Current Estimation through Magnetic Field Measurement,''''
IEEE Sensors Applications Symposium (SAS), pp.327-332, Mar. 2017.

Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``High Spatial Resolution Detection Method for Point Light Source in Scintillator'',
IS&T International Symposium on Electronic Imaging (EI), COIMG-418, Feb. 2017.

Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``CMOS-on-Quartz Pulse Generator for Low Power Applications,''
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.23-24, Jan. 2017.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
``A 15 x 15 SPAD Array Sensor with Breakdown-Pixel-Extraction Architecture for Efficient Data Readout,''
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.29-30, Jan. 2017.

Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``Resonant Power Supply Noise Reduction Using a Triangular Active Charge Injection,''
IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2016.

Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
``Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board'',
IEEE International Test Conference (ITC), Sess.14-1, Nov. 2016.

Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada,
``A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection Utilizing Built-in Offset Pulse,''
IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.313-316, Nov. 2016.

Tetsuya Iizuka, Norihito Tohge, Toru Nakura, Kunihiro Asada,
``A 4-Cycle-Start-Up Reference-Clock-Less All-Digital Burst-Mode CDR Based on Cycle-Lock Gated-Oscillator with Frequency Tracking'',
IEEE European Solid-State Circuit Conference (ESSCIRC), pp.301-304, Sept. 2016.

Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
``One Week TAT of 0.8um CMOS Gate Array with Analog Elements for Educational Exercise'',
IEEE European Workshop on Microelectronics Education (EWME), Sess.6-2, May 2016.

Parit Kanjanavirojkul, N.N.M.Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Analysis and Implementation of Quick Start Pulse Generator by CMOS Flipped on Quartz Substrate'',
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.3-6, May 2016.

Toru Nakura, Kunihiro Asada
``Fully Automated PLL Compiler Generating Final GDS from Specification'',
IEEE International Symbosium on Quality Electronic Design (ISQED), Sess. 6B, pp.437-442, March 2016.

Masahiro Kano, Toru Nakura, Kunihiro Asada,
``Analysis and Design of a Triangular Active Charge Injection for Stabilizing Resonant Power Supply Noise'',
IEEE International Symposium on Quality Electronic Design (ISQED), pp.386-391, Mar. 2016.

Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura Kunihiro Asada,
``Analytical Design Optimization of Sub-ranging ADC based on Stochastic Comparator'',
IEEE/ACM Design, Automation and Test in Europe (DATE), pp.517-522, Mar. 2016.

Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada,
``A Technique for Analyzing On-chip Power Supply Impedance'',
IEEE Asia Test Symposium (ATS), pp.193-198, Nov. 2015.

Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A Calibration-Free Time Difference Accumulator Using Two Pulses Propagating on a Single Buffer Ring'',
IEEE Asia Solid State Circuit Conference (ASSCC), pp.145-148, Nov. 2015.

Masamitsu Yoshizawa, Seisei Oyamada, Atsunori Hattori, Toru Nakura, Kunihiro Asada,
``Improvement of Power Integrity with Die-Attached Thin Film Capacitorsr'',
IEEE CPMT Symposium Japan (ICSJ), pp.183-186, Nov. 2015.

Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``Tracking PVT variations of Pulse Width Controlled PLL using Variable-Length Ring Oscillator'',
IEEE Nordic Circuits and Systems Conference (NORCAS), pp.1-4, Oct. 2015.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A CMOS SPAD Sensor Featuring Asynchronous Event-Extraction Readout Architecture for Faint Light Detection'',
JJAP Solid State Devices and Materials (SSDM), Sess.F-1-4, Sept. 2015.

Val Mikos, Toru Nakura, Kunihiro Asada,
``Non-Linearity Analysis of Stochastic Time-to-Digital Converter'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.171-176, July 2015.

Masahiro Kano, Toru Nakura, Kunihiro Asada,
``Resonant Power Supply Noise Cancelling with Noise Detector based in DLL and Vernier TDC'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.192-196, July 2015.

Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada,
``An On-chip Transfer Function Measurement of PLLs with Triangular Modulated Stimulus'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.192-196, July 2015.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors'',
IEEE Symposium on Design and Diagnostics of Electronics Circuit and System (DDECS), April 2015.

Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Seisei Oyamada, Atsunori Hattori, Kunihiro Asada
``Resonant Power Supply Noise Reduction using On-Die Decoupling Capacitors Embedded in Organic Interposer'',
IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Sess. M-III.7, Dec. 2014.

Masamitsu Yoshizawa, Seisei Oyamada, Atsunori Hattori, Toru Nakura, Kunihiro Asada,
``Improvement of Power Integrity with Thin Film Capacitors Embedded in Organic Interposer'',
IEEE CPMT Symposium Japan (ICSJ), Sess.11-3, Nov. 2014.

Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada,
``Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills'',
IEEE International Test Conference (ITC), Sess.8-2, Oct. 2014.

Y. Yakubo, S. Nagatsuka, S. Matsuda, S. Hondo, Y. Hata, Y. Okazaki, Y. Yamamoto, M. Nagai, M. Sakakura, T. Nakura, Y. Yamamoto, S. Yamazaki,
``High-speed and Lowleakage Characteristics of 60-nm C-axis Aligned Crystalline Oxide Semiconductor FET with GHz-ordered Cutoff Frequency'',
JJAP Solid State Devices and Materials (SSDM), Sess.E-7-1, Sept. 2014.

Masamitsu Yoshizawa, Seisei Oyamada, Atsunori Hattori, Toru Nakura, Kunihiro Asada,
``Power Integrity with Thin Film Decoupling Capacitors Embedded in Organic Interposer'',
Electronic Circuits World Convention (ECWC), No,53, pp.123-125, May 2014.

Toru Nakura, Kunihiro Asada
``Streaming Distribution of a Live Seminar: Rudimentary Knowledge for LSI Design'',
IEEE European Workshop on Microelectronics Education (EWME), Sess.4-1, pp.133-136, May 2014.

Kevin Ngari, Toru Nakura, Kunihiro Asada,
``Numerical and Theoretical Analysis on Voltage and Time Domain Dynamic Range of Scaled CMOS Circuits'',
IEEE Symposium on Design and Diagnostics of Electronics Circuit and System (DDECS), pp.282-285, April 2014.

Parit Kanjanavirojkul, Toru Nakura, Kunihiro Asada,
``Burst-Pulse Generator based on Transmission Line'',
IEEE Symposium on Design and Diagnostics of Electronics Circuit and System (DDECS), pp.59-64, April 2014.

Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A Pulse Width Controlled PLL and its Automated Design Flow'',
IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 5-8, Dec. 2013.

Tomohiko Yano, Toru Nakura, Kunihiro Asada,
``Low Pass Filter-less Pulse Width Controlled PLL with Zero Phase Offset Using Pulse Width Accumulator'',
IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 625-628, Dec. 2013.

Toru Nakura, Kunihiro Asada
``Pulse Width Controlled PLL/DLL using Soft Thermometer Code'',
IEEE Asia Solid State Circuit Conference (ASSCC), pp.345-348, Nov. 2013.

Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada,
``An All-Digital Time Difference Hold-and-Replication Circuit utilizing a Dual Pulse Ring Oscillator'',
IEEE Custom Integrated Circuits Conference (CICC), Sess.M-1, Sep. 2013.

Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada,
``Power Integrity Control of ATE for Emulating Power Supply Fluctuations on Customer Environment'',
IEEE International Test Conference (ITC 2012), Paper 7.3, Nov. 2012.

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
``Impact of All-Digital PLL on SoC Testing'',
IEEE Asia Test Symposium (ATS), Sess7B, pp.252-257, Nov. 2012.

Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
``7.5Vmax Arbitrary Waveform Generator with 65nm Standard CMOS under 1.2V Supply Voltage'',
IEEE Custom Integrated Circuits Conference (CICC), M-05, Sept. 2012.

Kunihiro Asada, Toru Nakura, Tetsuya Iizuka,
``Review and Future Prospects on Time-Domain Analog Approach'',
The second Solid-State Systems Symposium 2012 (4S-2012), Sess.2, Aug. 2012.

Makoto Ikeda, Tetsuya Iizuka, Satoshi Komatsu, Masahiro. Sasaki, Toru Nakura, Kunihiro Asada,
``Intelligent-PAD2.0: Platform for On-line SoC Health Condition Monitoring'',
European Workshop on Microelectronics Education (EWME 2012), Grenoble, May 2012.

Teruki Nakasato, Toru Nakura, Kunihiro Asada,
``Stress-Balance Flip-Flops for NBTI Tolerant Circuit based on Fine-Grain Redundancy'',
International SoC Conference (ISOCC), pp.150-153, Nov. 2011.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``On-Chip Resonant Supply Noise Reduction Utilizing Switched Parasitic Capacitors of Sleep Blocks with Tri-mode Power Gating Structure'',
IEEE European Solid-State Circuit Conference (ESSCIRC), pp.183-186, Oct. 2011.

Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada,
``An Automatic Phase control Circuit with DLL-like Architecture for Phased Array Antenna Systems'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), B1.1, pp.25-28, July. 2011.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction'',
IEEE Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.111-114, April. 2011.

Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter'',
IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.79-80, Jan. 2011.

Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``A Robust Pulse Delay Circuit Utilizing a Differential Buffer Ring'',
International SoC Design Conference (ISOCC), pp.272-275, Nov. 2010.

Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement'',
IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), Poster 2, Nov. 2010.

Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement Utilizing Buffer Ring with Pulse Counter'',
IEEE European Solid-State Circuits Conference (ESSCIRC), pp.182-185, Sep. 2010.

Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Time-to-Digital Converter Based on Time Difference Amplifier with Non-Linearity Calibration'',
IEEE European Solid-State Circuits Conference (ESSCIRC), pp.266-269, Sep. 2010.

Yuki Tamaki, Toru Nakura, Makoto Ikeda, and Kunihiro Asada,
``A Toggle-Type Peak Hold Circuit for Local Power Supply Noise Detection'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.29-32, Aug. 2010.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks'',
IEEE/JSAP Symposium on VLSI Circuit, pp.119-120, Jun. 2010.

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada,
``Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks'',
IEEE SSCS Kansai Chapter, June. 2010.

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS'',
IEEE Mediterranean Electrotechnical Conference (MELECON), pp.280-285, April 2010.

Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability and Aging Effects'',
IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.167-172, Apr. 2010.

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Cascaded Time Difference Amplifier Using Differential Logic Delay Cell'',
IEEE Asia Pacific Design Automation Conference (ASP-DAC), pp.355-356, Jan. 2010.

Devlin Benjamin Stefan, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Throughput optimization by pipeline alignment of a Self Synchronous FPGA'',
IEEE Field Programmable Technology (FPT), pp.312-315, Dec. 2009.

Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Cascaded Time Difference Amplifier Using Differential Logic Delay Cell'',
IEEE International SoC Design Conference (IOSCC), pp.194-197, Nov. 2009.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Ring Oscillator Based Random Number Generator Utilizing Wake-Up Time Uncertainty'',
IEEE Asian Solid-State Circuits Conference (ASSCC), pp.121-124, Nov. 2009.

Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All Digital Wireless Transceiver Using Modified BPSK and 2/3 Sub-sampling Technique'',
IEEE Application Specific Integrated Circuits Conference (ASICON), pp 469-472, Oct. 2009.

Benjamin Devlin, Jeong MyeongGyu, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``647 MHz, O.642pJ/block/cycle 65nm Self Synchronous FPGA'',
IEEE European Solid State Circuit Conference (ESSCIRC), pp.156-159, Sept. 2009.

Toru Nakura, Yutaro Tatemura, Gorschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada,
``SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults'',
IEEE European Conference On Circuit Theory and Design (ECCTD), pp.643-647, Sept. 2009.

Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada,
``Time Difference Amplifier Using Closed-Loop Gain Control '',
JSAP/IEEE Symposium on VLSI Circuits, sess.20-2, pp.208-209, June 2009.

Shingo Mandai, Toru Nakura, Makoto Ikeda Kunihiro Asada,
``Ultra High Speed 3-D Image Sensor'',
International Image Sensor Workshop (IISW), Sess.8-3, June 2009.

MyeongGyu Jeon, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature'',
ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.177-180, May 2009.

Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda,
``Measurement of Power Supply Noise Tolerance of Self-Timed Processor''
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.128-131, April 2009.

Bushnaq Sanad, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All digital baseband 50 Mbps data recovery using 5x oversampling with 0.9 data unit interval clock jitter tolerance'',
IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp.206-209, April 2009.

Shingo Mandai, Taihei Momma, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip'',
International SoC Conference (ISOCC), pp.89-92. 2008.

JinMyong Kim, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Variation Tolerant Transceiver Design For System-on-Glass'',
European Solid-State Circuits Conference (ESSCIRC), Poster, Sept. 2008.

Toru Nakura, Koichi Nose, Masayuki Mizuno,
``Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops'',
International Solid-State Circuits Conference (ISSCC), pp.402-403, Feb. 2007.

Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada,
``LAGS System Using Data/Instruction Grain Power Control'',
International Solid-State Circuits Conference (ISSCC), pp.66-67, Feb. 2007.

Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Design of Active Substrate Noise Canceller using Power Line di/dt Detector'',
IEEE Asia and South Pacific Deasign Automation Conference (ASP-DAC), Sess.1D-5, pp.100-102, Jan. 2007.

Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector'',
IEEE Asian Solid-State Circuits Conference (A-SSCC), Sess.8-3, pp.239-241, Oct. 2006.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector IP for Power Supply'',
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), pp.160-164, Dec. 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Autonomous di/dt Noise Control Scheme for Margin Aware Operation '',
IMEP/LETI European Solid-State Circuit Conference (ESSCIRC), Sess.8.G.2, pp.467-470, Sept. 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Feedforward Active Substrate Noise Cancelling Technique using Power Supply di/dt Detector '',
JSAP/IEEE Symposium on VLSI Circuits, Sess.18-4, pp.284-287, June 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Design and Measurement of On-chip di/dt Detector Circuit for Power Supply Line'',
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC) University Design Forum, Sess.16-12, pp.4\ 26-427, August 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Preliminary Experiments for Power Supply Noise Reduction using Stubs'',
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Sess.13-7, pp.286-289, August 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Power Supply di/dt Measurement using On-chip di/dt Detector Circuit'',
IEEE/JSAP Symposium on VLSI Circuits, Sess.7-4, pp.106-109, June 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit for Power Supply Line'',
IEEE International Conference on Microelectronic Test Structure (ICMTS), Sess.1-4, pp.19-22, March 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Theoretical Study of Stubs for Power Line Noise Reduction'',
IEEE Custom Integrated Circuits Conference (CICC), Sess.31-4, pp.715-718, Sept. 2003. [Proceeding] [Slides]

K. Yoshimura, Kimio Ueda, Toru Nakura, K. Kubo, Koichiro Mashiko, K. S. Maeda, Shigeru Maegawa, Y. Yamaguchi, Yoshio Matsuda,
``A 1.8 V 2.5 GHz PLL using 0.18 μm SOI/CMOS technology'',
IEEE SOI Conference, pp.12-13, Oct. 1999. [Proceeding]

Toru Nakura, Kimio Ueda, Kazuo Kubo, Warren Fernandez, Yoshio Matsuda, Koichiro Mashiko,
``A 3.6Gb/s 340-mW 16:1 Pipe-Lined Multiplexer using SOI-CMOS Technology'',
JSAP/IEEE Symposium on VLSI Circuits, Sess.3-4, pp.27-31, June 1999. [Proceeding]

Kimio Ueda, Toru Nakura, Yoshio Wada, Shigeru Maeda, Koichiro Mashiko,
``A 2.0Gbps multiplexer and a 2.7Gbps demultiplexer using 0.35um SOI/CMOS technology'',
European Solid-State Circuits Conference (ESSCIRC), pp.22-24, Sept. 1998. [Proceeding]

Toru Nakura, Kenji Sato, Masaki Funabashi, Geert Morthier, Roel Baets, Yoshiaki Nakano, Kunio Tada,
``First observation of changing coupling coefficients in a gain-coupled DFB laser with absorptive grating by automatic parameter extraction from subthreshold spectra'',
APS/IEEE/OSA Conference on Lasers and Electro-Optics (CLEO'97), CThM1, pp.136, May 1997. [Proceeding]

Yoshiaki Nakano, Masaki Funabashi, R. Yatsu, Toru Nakura, Kunio Tada,
``Characterization of excess noise induced by external reflection in 1.55um gain-coupled DFB lasers of absorptive grating type'',
IEEE International Conference on Integrated Optics and Optical Fiber Communications, , Sess.22-25, pp.25-28, Sept. 1997. [Proceeding]

Masaki Funabashi, H. Kawanishi, Tsurugi K. Sudoh, Toru Nakura, D. Schmitz, F. Schulte, Yoshiaki Nakano, Kunio Tada,
``Comparision of InGaAs absorptive grating structures in 1.55 μm InGaAsP/InP strained MQW gain-coupled DFB lasers'',
IEEE International Conference on Indium Phosphide and Related Materials, , Sess.11-15, pp.292-295, May 1997. [Proceeding]




国内会議 (Domestic Conference Presentations)


寺尾直樹, 名倉徹, 石田雅裕, 池野理門, 日下崇, 飯塚哲也, 浅田邦博,
``LSIテストに向けた電源インピーダンス模擬,''
電子情報通信学会総合大会, A-1-3, 2017年3月.

Xiao Yang, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A 31x31 SPAD Array Sensor with Variable Readout Time for Scintillation Light Detection,''
電子情報通信学会 ソサイエティ大会, C-12-11, 2016年9月.

Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Microwave Pulse Generator based on Current-Mode Trigger and On-Quartz Transmission Line,''
電子情報通信学会 ソサイエティ大会, C-2-26, 2016年9月.

Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Fine-Resolution Light Source Position Estimation Method for Scintillation Detector,''
電子情報通信学会 ソサイエティ大会, B-20-28, 2016年9月.

織田 勇冴, 飯塚 哲也, 名倉 徹, 浅田 邦博,
``表面磁界観測による電流推定を用いた集積回路の電源網解析,''
情報処理学会 DAシンポジウム, pp.85-90, 2016年9月.

Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
``A 15x15 SPAD Sensor Featuring Breakdown Pixels Extraction Architecture for Efficient Data Readout'',
IEICE LSI and Systems Workshop, Poster 14, May 2016.

Parit Kanjanavirojkul, N.N.M Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``An X-band CMOS-on-Quartz Pulse Generator for Low Power Application'',
IEICE General Conference, C-12-7, May 2016.

古賀 丈尚, 飯塚 哲也, 名倉 徹, 浅田 邦博,
``高分解能パルス縮小型時間-デジタル変換器の設計'',
電子情報通信学会 技術研究報告,pp.1-6, 2015年12月.

峠 仁人, 飯塚 哲也, 名倉 徹, 三浦 賢, 村上 芳道, 浅田 邦博,
``フラクショナル位相選択法によりジッタ特性を改善した高速起動完全デジタルCDR回路の設計'',
電子情報通信学会 技術研究報告,pp.17-22, 2015年12月.

都井 敬,名倉 徹,飯塚 哲也,浅田 邦博,
``Hill-Climbing法を用いたパルス幅制御PLLのPVTばらつきへの自動適応'',
電子情報通信学会 技術研究報告,pp.135-140, 2015年12月.

矢野 智比古,名倉 徹,飯塚 哲也,浅田 邦博,
``バッファリングを利用した出力ドリフト補正が不要な時間領域アナログ信号積分器'',
電子情報通信学会 技術研究報告,pp.129-134, 2015年12月.

モハンマド マルフ ホサイン,飯塚 哲也,名倉 徹,浅田 邦博,
``統計的コンパレータを用いたアナログ-ディジタル変換回路の性能解析'',
電子情報通信学会 技術研究報告,pp.128-128, 2015年12月.

吉川俊之, 名倉徹, 浅田邦博,
``三角波変調を用いたPLL帯域幅の校正手法'',
電子情報通信学会 ソサイエティ大会,C-12-23, 2015年9月.

Parit Kanjanavirojkul, N.N.M Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``A Transmission Line Based Pulse Generator on 0.18-um CMOS over Quartz Substrate'',
IEICE Society Conference, C-2-4, Sep. 2015.

鹿野 真弘, 名倉 徹, 浅田 邦博,
``動的制御による電源共振ノイズ低減における電荷注入最適化手法'',
電子情報通信学会 LSIとシステムのワークショップ,Poster 15, 2015年5月.

吉川俊之, 名倉徹, 浅田邦博,
``三角波変調を用いたPLL帯域幅のオンチップ測定手法'',
電子情報通信学会 ソサイエティ大会,Poster 7, 2015年5月.

Parit Kanjanavirojkul, N.N.M. Khanh, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``A Transmission Line Pulse Generator Towards Sub-MMW on 0.18um CMOS over FR-4 substrate,''
電子情報通信学会 総合大会論文集, C-2-19, 2015年3月.

Xiao Yang, Honbo Zhu, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``Single Avalanche Photo Diode using Standard CMOS Technology,''
電子情報通信学会 総合大会論文集, C-2-19, 2015年3月.

森 一倫, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``NBTI の周波数依存性を利用した劣化過渡解析の高速化手法,''
電子情報通信学会 総合大会論文集, A-2-29, 2015年3月.

森 一倫, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``論理シミュレーションにもとづいたNBTI劣化過渡解析の高速化手法,''
電子情報通信学会研究報告会集積回路研究会(ICD2014), pp.141-145, 2014年12月.

Kevin Ngari Muriithi, 飯塚 哲也, 名倉 徹, 浅田 邦博,
``Effect of CMOS Device Scaling on Time-domain and Voltage-domain Dynamic Range,''
電子情報通信学会 ソサイエティ大会論文集, C-12-40, 2013年9月.

松井 裕明, 名倉 徹, 浅田 邦博,
``電波エナジーハーベスティング実現のための基板バイアス効果を用いた整流器,''
電子情報通信学会 ソサイエティ大会論文集, C-12, 2013年9月.

久保田 透, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``単一光子アバランシェダイオードアレイを用いたシンチレータ内の発光軌跡観測,''
電子情報通信学会 総合大会論文集, C-1-18, 2013年3月.

齊藤 総, 名倉 徹, 飯塚 哲也, 池田 誠, 浅田 邦博,
``アクティブチャージシェアリングを用いた DVS における電源共振ノイズの低減,''
STARC シンポジウム, Poster, 2013年1月.

齊藤 総, 名倉 徹, 飯塚 哲也, 浅田 邦博,
``動的電源電圧制御におけるアクティブチャージシェアリングを用いた電源共振ノイズの低減,''
電子情報通信学会 ソサイエティ大会論文集, C-12-41, 2012年9月.

児玉 和俊, 飯塚 哲也, 名倉 徹, 浅田 邦博,
``制御信号の周期内切替によるデジタル制御発振器の高解像度化,''
電子情報通信学会 LSIとシステムのワークショップ, 2012年5月.

吉川 俊之, 名倉 徹, 浅田 邦博,
``フェーズドアレイシステムにおける回路へのばらつきの影響,''
電子情報通信学会 総合大会論文集, C-12-71 2012年3月.

中里 輝樹, 名倉 徹, 浅田 邦博,
``細粒度二重化を用いた耐 回路のためのストレスバランスフリップフロップ,''
電子情報通信学会 総合大会論文集, D-10-2 2012年3月.

吉川 俊之, 名倉 徹, 浅田 邦博,
``フェーズドアレイシステムにおける位相差校正回路'',
電子情報通信学会ソサイエティ大会, C-12-28, 2011年9月.

金 鎮明, 名倉 徹, 高田 英裕, 石橋 孝一郎, 池田 誠, 浅田 邦博,
``アクティブデキャップを用いた電源共振雑音低減手法'',
電子情報通信学会技術研究報告, pp.66-72, 2011年7月.

程 在鉉, 飯塚 哲也, 名倉 徹, 池田 誠, 浅田 邦博,
``小面積ディジタルプロセスばらつきモニタの特性評価'',
電子情報通信学会ソサイエティ大会講演論文集, pp.84, C-12-232, 2010年8月.

金 鎮明, 名倉 徹, 高田 英裕, 石橋 孝一郎, 池田 誠, 浅田 邦博,
``複数IPコア回路におけるスリープブロックの寄生容量を用いたチップ内電源共振雑音低減手法'',
電子情報通信学会技術研究報告, pp.1-4, 2010年8月.

飯塚 哲也, 名倉 徹, 浅田 邦博,
``PMOS/NMOSのプロセスばらつきを独立に検出するためのリング型バッファチェインを用いたオンチップモニタ'',
電子情報通信学会技術研究報告, pp.15-20, 2010年7月.

程 在鉉, 飯塚 哲也 ,名倉 徹, 池田 誠, 浅田 邦博,
``インバータチェーンを用いたパルス幅メモリ'',
電子情報通信学会総合大会講演論文集, pp.116, C-12-39, 2010年03月.

萬代 新悟, 名倉 徹, 池田 誠, 浅田 邦博,
``差動遅延素子を用いたカスケード型時間増幅器'',
電子情報通信学会総合大会講演論文集, C-12-16, 2010年03月.

Ngoc Lan Dang, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Digital Substrate Noise Cancelling Method using Active Guard Ring'',
電子情報通信学会総合大会講演論文集, C-12-67, 2010年03月.

名倉 徹, 萬代 新悟, 池田 誠, 浅田邦博,
``フィードバック制御を用いた時間差増幅回路'',
電子情報通信学会研究報告集積回路研究会, ICD2009-46, pp.69-74, 2009年10月.

萬代 新悟, 名倉 徹, 池田 誠, 浅田 邦博,
``時間差増幅器を用いた高解像度時間差ディジタル変換'',
2009年電子情報通信学会ソサイエティ大会, C-12-33, 2009年9月.

萬代 新悟, 名倉 徹, 池田 誠, 浅田 邦博,
``多機能デュアルイメージゃコアチップ'',
2009年LSIとシステムのワークショップ, Poster, 2009年5月.

萬代 新悟, 名倉 徹, 池田 誠, 浅田 邦博,
``適応型行並列走査三次元イメージセンサ'',
2009年電子情報通信学会総合大会, C-12-72, 2009年3月.

金 江南, 名倉 徹, 池田 誠, 浅田 邦博,
``スキューを用いた高精度の光学的ポジションセンサー'',
2009年電子情報通信学会総合大会, A-1-19, 2009年3月.

金 鎮明, 猪飼 啓太, 名倉 徹, 池田 誠, 浅田 邦博,
``ばらつきに強い近接トランシーバー回路'',
2008年電子情報通信学会ソサイエティ大会, B-5-34, 2008年9月.

大塚 泰雅, 佐々木 昌浩, 名倉 徹, 池田 誠, 浅田 邦博,
``Time-of-Flight法に向けたMAGFETの試作及び検討'',
2008年電子情報通信学会ソサイエティ大会, C-12-62, 2008年9月.

風間 大輔, 名倉 徹, 池田 誠, 浅田 邦博,
``複数di/dt検出回路を用いた基板ノイズ低減手法'',
2006年電子情報通信学会ソサイエティ大会, C-12-22, 2006年9月.

名倉 徹, 風間 大輔, 池田 誠, 浅田邦博,
``di/dt 検出回路を用いた基板ノイズ低減の最適化'',
電子情報通信学会研究報告集積回路研究会, ICD2007-139, pp.11-16, 2007年11月. [Proceeding] [Slides]

風間 大輔, 名倉 徹, 池田 誠, 浅田 邦博,
``複数di/dt検出回路を用いた基板ノイズ低減手法'',
2006年電子情報通信学会ソサイエティ大会, C-12-22, pp.83, 2006年9月.

名倉 徹, 池田 誠, 浅田 邦博,
``LSI電源用di/dt測定回路コア'',
第7回 LSI IP デザインアワード, 2005年5月. [Proceeding] [Slides]

名倉 徹, 池田 誠, 浅田 邦博,
``オフチップスタブを用いたLSIにおける電源ノイズ低減'',
2004年電子情報通信学会ソサイエティ大会, C-12-1, pp.71, 2004年9月. [Proceeding] [Slides]

名倉 徹, 池田 誠, 浅田 邦博,
``スタブを用いた電源安定化手法'',
電子情報通信学会デザインガイア, p.217-222, 2003年11月. [Proceeding] [Slides]

申 秀擘, 名倉 徹, 池田 誠, 浅田 邦博,
``エラー伝搬に基づいた信頼性評価'',
2003年電子情報通信学会ソサイエティ大会, C-12-6, 2003年9月.

名倉 徹, 廣田 尊則, 上田 公大, 益子 耕一郎, 浜野 尚徳,
``ボディ電圧制御型SOIゲートアレイを用いた0.5V 320MHz 8ビット MUX/DEMUX'',
電子情報通信学会研究報告集積回路研究会, ICD98-121, pp.67-74, 1998年8月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(IV)'',
春期第44回応用物理学関連連合講演会, 29p-PA-11, 1997年3月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの結合係数自動抽出プログラム'',
電子情報通信学会エレクトロニクスソサイエティ大会, C-315, 1996年9月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(III)'',
秋期第57回応用物理学会学術講演会, 9a-KH-4, 1996年9月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(II)'',
春期第43回応用物理学関連連合講演会, 27a-C-1, 1996年3月. [Proceeding]

名倉 徹, 池野 理門, 浅田 邦博,
``薄膜SOIにおけるバックゲート効果の解析モデル'',
春期第42回応用物理学関連連合講演会, 29p-K-19, 1995年3月. [Proceeding]




Invited Talk, Tutorial


Toru Nakura,
``[Invited] Time Difference Amplifier and Its Application for TDC'',
JSAP International Conference on Solid State Devices and Materials (SSDM), Sept. 2014.

Toru Nakura,
``[Invited] Numerical and Theoretical Analysis on Voltage and Time Domain Dynamic Range of scaled CMOS Circuits'',
D2T Symposium, Aug. 2014.

Toru Nakura,
``[Invited] Time Difference Amplifier and Its Application for TDC'',
IEEE SSCS UAE Chapter Seminar, Dec. 2013.

Toru Nakura,
``[Tutorial] Very Basics of IO Buffers'',
International Conference on Microelectronic Test Structures (ICMTS), March 2013.

Toru Nakura,
``[Invited] On-Chip di/dt Detector and Autonomous di/dt Noise Control for Power Supply'',
World Congress of Emerging Info Tech (WCEIT), pp.053, Aug. 2012.

Toru Nakura,
``[Invited] Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Block'',
10th Taiwan-Japan Microelectronics Symposium, Oct. 2010.

``[Panel Discussion Coordinator] Are you ready for More-than-Moore?'',
9th Japan-Taiwan Microelectronics Symposium, Sept., 2009




招待講演、チュートリアル


名倉 徹,
``[チュートリアル] 時間-デジタル変換回路(TDC)と時間差増幅回路(TDA)'',
大阪大学 先端アナログ技術セミナー, 2016年2月.

名倉 徹,
``[招待講演] LSI 設計常識講座 〜配線 RC 抽出と IO バッファ〜'',
日本学術振興会 VLSI 夏の学校, 2012年8月.

名倉 徹,
``[招待講演] 時間差増幅回路の発想から発表まで'',
電子情報通信学会研究報告集積回路研究会, ICD2010-117, pp.107-111, 2010年12月.

名倉 徹, 池田 誠, 浅田 邦博,
``[招待講演] 回路設計技術の最新動向'',
第18回エレクトロニクス実装学術講演大会, p.131-132, 2004年3月




レクチャー等


Toru Nakura,
``[Lecture] Analog+1'',
ICDREC, May. 2014.

Toru Nakura,
``[Lecture] VDEC Introduction & Low Pass Filter-less Pulse Width Controlled PLL'',
UAE Visit @ Kharifa University, Dec. 2013.

Toru Nakura,
``[Lecture] Time Difference Amplifier and Random Number Generator'',
Taiwan Visit @ National Ilan University (宣蘭大), Nov. 2009.




受賞 (Award)


Parit Kanjanavirojkul, Nguyen Ngoc Mai-Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Impulse Signal Generator based on Current-Mode Excitation and Transmission Line Resonator,''
IEEE New Circuit and System Conference (NEWCAS), pp.257-260, June. 2017.
Best Student Paper Award

Yuki Oda, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada,
``Analysis of VLSI Power Supply Network based on Current Estimation through Magnetic Field Measurement,''
IEEE Sensors Applications Symposium (SAS), pp.327-332, Mar. 2017.
Student Travel Grand Award

織田 勇冴, 飯塚 哲也, 名倉 徹, 浅田 邦博,
``表面磁界観測による電流推定を用いた集積回路の電源網解析,''
情報処理学会 DAシンポジウム, pp.85-90, 2016年9月.
SLDM 研究会優秀発表学生賞

峠 仁人, 飯塚 哲也, 名倉 徹, 三浦 賢, 村上 芳道, 浅田 邦博,
``フラクショナル位相選択法によりジッタ特性を改善した高速起動完全デジタルCDR回路の設計'',
電子情報通信学会 技術研究報告,pp.17-22, 2015年12月.
ICD 研究会優秀若手講演

Toru Nakura, Kunihiro Asada,
``Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter'',
IEICE Trans. on Electronics, Vol.E95-C No.2, pp.297-302, March 2012.
電子情報通信学会 平成 24 年度 論文賞

Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada,
``An Automatic Phase control Circuit with DLL-like Architecture for Phased Array Antenna Systems'',
IEEE Asia Symposium on Quality Electronic Design (ASQED), Sess.B1.1, July. 2011.
Student Best Paper Award

Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``All Digital Wireless Transceiver Using Modified BPSK and 2/3 Sub-sampling Technique'',
IEEE Application Specific Integrated Circuits Conference (ASICON), pp 469-472, Oct. 2009.
Student Best Paper Award

Shingo Mandai, Taihei Momma, Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip'',
International SoC Conference (ISOCC), pp.89-92. Oct. 2008.
Student Best Paper Award

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector IP for Power Supply'',
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), pp.160-164, Dec. 2005.
Best Paper Award

名倉 徹, 池田 誠, 浅田 邦博,
``LSI 電源用 di/dt 測定回路コア'',
第 7 回 LSI IP デザインアワード, 5 月, 2005
IP 最優秀賞

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit'',
IEICE Trans. on Electronics, Vol.E88-C No.5, pp.782-787, May 2005.
電子情報通信学会 平成 17 年度 論文賞




国際特許 (International Patent)


Toru Nakura, Masahiro Ishida, Takashi Kusaka, Rimon Ikeno, Naoki Terao, Kunihiro Asada,
``Power Supply Apparatus'',
Submitted. (USA)

Toru Nakura, Satoshi Komatsu, Masahiro Ishida, Kunihiro Asada,
``Testing Device and Obtaining Test Conditions'',
Submitted. (USA and Korea)

Toru Nakura, Kunihiro Asada,
``Signal Conversion Circuit, PLL Circuit, Delay Adjustment Circuit, and Phase Control Circuit'',
PCT/JP2012/063206

Toru Nakura, Masayuki Mizuno, Koichi Nose,
``Failure Prediction Circuit and Method, and Semiconductor Integrated Circuit'',
US 2010/0251046 A1, September 30, 2010 (USA)

Toru Nakura, Kmio Ueda,
``Fast operating multiplexer'',
6477186, November 5, 2002 (USA)

Toru Nakura, Kmio Ueda,
``Semiconductor device with reduced transistor leakage current'',
6472712, October 29, 2002 (USA)

Toru Nakura, Kmio Ueda,
``Synchronous frequency dividing circuit'',
6249157, June 19, 2001 (USA)

Toru Nakura, Kmio Ueda,
``Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing varous types of surge'',
6208494, March 27, 2001 (USA)

Toru Nakura, Kmio Ueda,
``Counter circuit'',
6101233, August 8, 2000 (USA)




国内特許 (Domestic Patent)


飯塚 哲也, 名倉 徹, 峠 仁人, 浅田 邦博, 三浦 賢, 村上 芳道,
``クロック生成装置およびクロックデータ復元装置'',
2016年1月21日出願

名倉 徹, 石田 雅裕, 日下 崇, 池野 理門, 浅田 邦博, 寺尾 直樹,
``電源装置およびそれを用いた試験装置、電源電圧の供給方法'',
特願2016-014282, 2016年1月28日出願

飯塚 哲也, 古賀 丈尚, 名倉 徹, 浅田 邦博,
``時間デジタル変換方法および時間-デジタル変換装置'',
特願2016-007517, 2016年1月19日出願

名倉 徹, 浅田 邦博, 飯塚 哲也, 久保田 透,
``光子検出装置および放射線測定装置,''
特願2013-091997, 特開2014-215145.

名倉 徹, 石田 雅裕, 小松 聡, 浅田 邦博,
``試験装置および試験条件の取得方法'',
特開2014-074622, 2014年4月

名倉 徹, 石田 雅裕, 日下 崇, 浅田 邦博, 小松 聡, 吉川 俊之,
``電源装置、それを用いた試験装置、電源電圧の制御方法'',
特開2014-074621, 2014年4月

名倉 徹, 浅田 邦博,
``信号変換回路、PLL 回路、遅延調整回路及び位相制御回路'',
PCT/JP2012/063206

石田 雅裕, 名倉 徹, 小松 聡, 浅田 邦博,
``試験装置'',
特開2013-088146, 2013年5月

名倉 徹, 浅田 邦博, 飯塚 哲也, 久保田 透
``光子検出装置および放射線測定装置'',
特開2014-215145, 2008年8月

飯塚 哲也, 程 在鉉 名倉 徹, 池田 誠, 浅田 邦博,
``電流特性検出回路およびウェル電圧調整回路'',
特開2011-166222, 2011年8月

金 鎮明, 名倉 徹, 高田 英裕, 石橋 孝一郎, 池田 誠, 浅田 邦博,
``半導体集積回路装置'',
特開2011-151518, 2011年8月

池田 誠, 名倉 徹, 野瀬 浩一, 水野 正之, 浅田 邦博,
``半導体集積回路および動作条件制御方法'',
特開2008-192040, 2008年8月

名倉 徹, 水野 正之, 野瀬 浩一,
``故障予測回路と方法及び半導体集積回路'',
再公開08-023577, 2008年2月

名倉 徹, 上田 公大,
``マルチプレクサ'',
特開2000-278141, 2000年12月

名倉 徹, 上田 公大,
``分周回路'',
特開2000-224026, 2000年8月

名倉 徹, 上田 公大,
``半導体装置およびその製造方法'',
特開2000-223701, 2000年8月

名倉 徹, 上田 公大,
``半導体集積回路装置'',
特開2000-012788, 2000年1月

名倉 徹, 上田 公大,
``カウンタ回路'',
特開平11-330951, 1999年11月




著書


アナログ RF CMOS 集積回路設計 応用編 [培風館] (第 12 章, 第 13 章, 第 22 章)
LSI 設計常識講座 [東京大学出版会]
Essential Knowledge for Transistor-Level LSI Circuit Design [Springer]



卒業論文・修士論文・博士論文 (Bachelor, Master and Ph.D Thesis)


Toru Nakura, (Superviser) Kunihiro Asada,
``A Study on Power Line Noise Reduction in Large Scale Integration'',
For the degree of Doctor of Philosophy, Department of Electronic Engineering, the University of Tokyo, December 2004. [Paper] [Handout] [Slides]

名倉 徹, (指導教官) 中野 義昭,
``分布帰還型半導体レーザにおける閾値下スペクトルからのパラメータ抽出'',
東京大学大学院工学系研究科電子工学専攻 修士論文, 1997年2月 [PDF File]

名倉 徹, (指導教官) 浅田 邦博,
``薄膜SOIにおけるバックゲート効果'',
東京大学工学部電子工学科 卒業論文, 1995年2月 [PDF File]


起業


株式会社アイカデザイン設立 (2013年)



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