Publication List

Technical Journals

[1] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits," IEICE Transactions on Electronics, vol. E87-C, no. 6, pp. 1069-1077, June 2004.

[2] H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, "A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture," IEICE Transactions on Electronics, vol. E87-C, no. 2, pp. 238-245, Feb. 2004.

[3] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers," IEICE Transactions on Electronics, vol. E84-C, no. 9, pp. 1240-1246, Sept. 2001.

Proceedings of International Conferences

[1] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed Logic Circuit Family with Interdigitated Array Structure for Deep Sub-Micron IC Design," Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 189-192, Portugal, Sept. 2003.

[2] H. Yamaoka, H. Yoshida, M. Ikeda, and K. Asada, "A Dual-Rail PLA with 2-Input Logic Cells," Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 203-206, Italy, Sept. 2002.

[3] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed Functional Memory with a Capability of Hamming-Distance-Based Data Search by Dynamic Threshold Logic Circuits," Proceedings of European Solid-State Circuits Conference (ESSCIRC), pp. 667-670, Italy, Sept. 2002.

[4] H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada, "Logic Synthesis for PLA with 2-input Logic Elements," Proceedings of International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 373-376, United States, May 2002.

[5] H. Yoshida, H. Yamaoka, M. Ikeda, and K. Asada, "Logic Synthesis for AND-XOR-OR Sense-Amplifying PLA," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) and International Conference on VLSI Design, pp. 166-171, India, Jan. 2002.

[6] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed PLA Using Array Logic Circuits with Latch Sense Amplifiers and a Charge Sharing Scheme," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 3-4, Yokohama, Jan. 2001.

Proceedings of Domestic Conferences and Technical Society Meetings

[1] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed Functional Memory with a Capability of Hamming-Distance-Selective Data Search Using Threshold Logic Circuits," IEICE Technical Report, VLD2002-151, pp. 31-36, Campus Plaza Kyoto, Mar. 2003 (in Japanese).

[2] U. Ekinciel, H. Yamaoka, M. Ikeda, and K. Asada, "Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells," IEICE Technical Report, VLD2002-152, pp. 37-42, Campus Plaza Kyoto, Mar. 2003.

[3] U. Ekinciel, H. Yamaoka, M. Ikeda, and K. Asada, "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells," Proceedings of IEICE Society Conference 2002, C-3-7, Miyazaki University, Sept. 2002.

[4] H. Yamaoka, M. Ikeda, and K. Asada, "A Dual-Rail PLA with 2-Input Logic Cells," IEICE Technical Report, SDM2002-156, pp. 19-24, Future University-Hakodate, Aug. 2002 (in Japanese).

[5] H. Yoshida, H. Yamaoka, M. Ikeda and K. Asada, "Logic Synthesis for PLA with 2-input Logic Elements," IEICE Technical Report, CPSY2001-72, pp. 67-72, Hukuoka, Nov. 2001 (in Japanese).

[6] H. Yamaoka and K. Asada, "A Threshold Logic-Based High-Speed Hamming Distance Detector and Its Evaluation," IEICE Technical Report, SDM2001-134, pp. 37-42, Muroran Institute of Technology, Aug. 2001 (in Japanese).

[7] H. Yoshida, H. Yamaoka, M. Ikeda and K. Asada, "Logic Synthesis for XOR-Based Dual-Rail PLA," Proceedings of IPSJ DA Symposium, pp. 31-36, Shizuoka, Jul. 2001 (in Japanese).

[8] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed PLA with Latch Sense Amplifiers," Proceedings of IEICE 4th System LSI Biwako Workshop, pp. 223-226, Shiga, Nov. 2000 (in Japanese).

[9] H. Yamaoka, M. Ikeda, and K. Asada, "A High-Speed PLA with Latch Sense Amplifiers," Proceedings of IEICE General Conference 2000, C-12-16, p. 111, Hiroshima University, Mar. 2000 (in Japanese).

[10] T. Numa, R. Matsuo, H. Yamaoka, N. D. Minh, R. Saito, and T. Kimura, "A FPGA-Based Processor for Matrix Calculations," Proceedings of Physical Society of Japan (JPS), Autumn Sectional Meetings, 26pQ-2, Iwate University, Sept. 1999 (in Japanese).

Awards

[1] H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada, "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells," 5th Nikkei-BP LSI IP Design Award (IP Award), June 2003.

[2] H. Yamaoka, H. Yoshida, U. Ekinciel, and K. Asada, "A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells," 4th Nikkei-BP LSI IP Design Award (Challenge Award), May 2002.