- H. Yabe, and M. Ikeda
"CMOS Image Sensor for 3-D range map acquisition Using Time Encoded 2-D Structured Pattern,"
International Image Sensor Workshop, Hokkaido, Japan, Jun. 2011,
- T. J. Yamaguchi, M. Abbas, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, S. Komatsu, and K. Asada,
"An Equivalent-Time and Clocked Approach for Continuous-T ime Quantization,"
IEEE International Symposium on Circuits and Systems 2011 (ISCAS 2011), pp. 2529-2532,
May. 2011.
- J. Kim, T. Nakura, H. Takata, K. Ishibashi, M. Ikeda, and K. Asada,
"Decoupling Capacitance Boosting for On-Chip Resonant Supply Noise Reduction,"
in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 111-114,
Apr. 2011.
- T. Iizuka and K. Asada,
"An All-Digital On-Chip PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator,"
in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 115-120,
Apr. 2011.
- M. Ikeda,
"PVT and Aging Torelant Systems Employing Self-Synchronous Operation,"
Symposium LAAS/University of Tokyo GCOE Program : Secure Life Electronics, Mar. 2011.
- N.N.M. Khanh, M. Sasaki and K. Asada,
"A Fully Integrated Shock Wave Trasmitter with an On-chip Dipole Antenna for Pulse Beam-Formability in 0.18-μm CMOS,"
University Design Contest, 16th Asian and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Japan, pp. 107-108,Jan. 2011.
- J. Jeong, T. Iizuka, T. Nakura, M. Ikeda and K. Asada,
"All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter,"
in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 79-80,Jan. 2011.
- B.S. Devlin, M. Ikeda, and K. Asada,
"A Gate-level Pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS,"
in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 25-28, Jan. 2011.
- K. Asada,
"Solutions for Side Effect of Low Voltage Operation in Deep Sub‐micron VLSI Circuits,"
Plenary Talk in IEEE International SoC Design Conference 2011,Nov.2011.
- T. Nakasato, T. Nakura, and K. Asada,
"Stress-Balance Flip-Flops for NBTI Tolerant Circuit based on Fine-Grain Redundancy,"
in Proceedings of IEEE International SoC Design Conference (ISOCC), pp.150-153,Nov.2011.
- T. Kikkawa, T. Nakura, K. Asada
"An Automatic Phase Control Circuit for Phased Array Antenna Systems"
IEICE Society Conference, C-12-28, p. 103, Sep. 2011 , (in Japanese).
- H. Yabe, M. Ikeda
"3-D Range Map Acquisition System Based on CMOS Image Sensor"
Technical Group on Information Sensing Technologies, Sep. 2011 , (in Japanese).
- N.N.M. Khanh, M. Sasaki and K. Asada,
"Integrated Wideband Dipole Antenna for Pulse Beam-Fomability by Using 0.18μm CMOS Technology,"
Asia-Pacific Microwave Conference (APMC), Yokohama, Japan, pp. 1561-1564,Dec. 2010.
- T. Nakura
"Time difference amplifier, from getting idea to presenting at a conference,"
電子情報通信学会研究報告集積回路研究会, ICD2010-117, pp. 107-111,Dec.2010,
- M. Abbas, Y. Furukawa, S. Komatsu, T. J. Yamaguchi, and K. Asada,
"Clocked Comparator for High-Speed Applications in 65nm Technology,"
IEEE Asian Solid-State Circuits Conference 2010 (A-SSCC2010), pp. 277-280,Nov. 2010.
- J. Jeong, T. Iizuka, T. Nakura, M. ikeda and K. Asada,
"A Robust Pulse Delay Circuit Utilizing a Differential Buffer Ring,"
in Proceedings of International SoC Design Conference (ISOCC), pp. 272-275Nov. 2010.
- M. Ikeda,
"[Plenary Talk] Dependable System against PVT and Aging Employing Self-Synchronous Operation,"
ISOCC 2010, Nov. 2010.
- T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada,
"Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement,"
IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), San Jose, USA,Nov. 2010.
- M. Sasaki, N.N.M. Khanh, and Kunihiro Asada,
"A Circuit for on-Chip Skew Adjustment with Jitter and Setup Time Measurement,"
2010 IEEE Asian Solid-State Circuits Conference (ASSCC), Beijing, China, Nov. 2010.
- B.S. Devlin, M. Ikeda, and K. Asada,
"A 65nm 2.97GHz Self Synchronous FPGA with 42% Power Bounce Tolerance,"
in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 8-10, Nov. 2010.