- H. Yoshida, M. Ikeda, and K. Asada,
"An Algebraic Approach for Transistor Circuit Synthesis,"
in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
- M. Abbas, M. Ikeda, and K. Asada,
"On-Chip Non-Periodic High-Swing Noise Detector,"
in Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. --,Dec. 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
IEICE Technical Report, vol. 105, no. 442, pp. 79 - 84,Dec. 2005,
- H. Yoshida, M. Ikeda, and K. Asada,
"Exact Minimum Logic Factoring via Quantified Boolean Satisfiability,"
IEICE Technical Report, vol. 105, no. 443, pp. 41 - 46,Dec. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"On-chip di/dt Detector IP for Power Supply,"
IP Based SoC Design Conference & Exhibition (IP-SOC)Dec. 2005,(Best Paper Award).
- K. H. Dia, R. Zheng, M. Ikeda, and K. Asada,
"Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme,"
in Proc. of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 309 -- 312,Nov. 2005,
- M. Ikeda, Y. Yachide, Y. Oike, and K. Asada,
"Wavelength Identification Sensor Using MOS Photo-transistor Array Based on Metal Slit Diffraction,"
in Proc. of International Conference on Sensing Technology (ICST), pp. 683 -- 686,Nov. 2005,
- K. Yamamoto, M.Ikeda, and K. Asada,
"Stereo Vision with Random Pattern Light Projection,"
ITE Technical Report, vol. 29, no. 67, pp. 13 - 16,Nov. 2005,
- M. Abbas, M. Ikeda, and K. Asada,
"On-chip Detector for Non-Periodic High-Swing Noise Detection,"
in Proc. of International SoC Design Conference (ISOCC), pp. 231 -- 234,Oct. 2005,
- T.Kazama, M. Ikeda, and K. Asada,
"Shot Reduction Technique for Character Projection Lithography using combined cell stencil,"
in Proc. of SPIE BACUS Symposium on Photomask Technology, pp. 5992-5996,Oct. 2005,
- M. Abbas, M. Ikeda and K. Asada,
"On-chip Detector for Non-Periodic High-Swing Noise Sensing,"
in Proc. of International SOC Design Conference (ISOCC), pp.231-234,Oct. 2005,
- Y. Yachide, Y. Oike, M. Ikeda, and K. Asada,
"Real-Time 3-D Measurement System Based on Light-Section Method Using Smart Image Sensor,"
in Proc. of IEEE International Conference on Image Processing(ICIP), pp. 1008 -- 1011,Sep. 2005,
- N. Li, M. Ikeda, and K. Asada,
"Analysis of Low Noise ThreePhase Asynchronous Data Transmission,"
in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp. 479 -- 482,Sep. 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures,"
in Proc. of IPSJ DA Symposium 2005, pp. 121 -- 126,Aug. 2005,(IPSJ Yamashita SIG Research Award).
- T. Iizuka, M. Ikeda, and K. Asada,
"Computational Cost Reduction for Minimum-Width Transistor Placement of Arbitrary Circuit Structures,"
in Proc. of IPSJ DA Symposium 2005, pp. 121 - 126,Aug. 2005,
- H. Yoshida, M. Ikeda, and K. Asada,
"An Algebraic Approach for Synthesizing Circuits with Minimum Number of Transistors,"
in Proc. of IPSJ DA Symposium 2005, pp. 133 - 138,Aug. 2005,
- T. Nakura, M. Ikeda, and K. Asada,
"Feedforward Active Substrate Noise Cancelling Technique using Power Supply di/dt Detector,"
JSAP/IEEE Symposium on VLSI Circuits (VLSI Symp.) Dig. of Tech, Papers, pp. 284 -- 287,Jun. 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Transistor Placement Without Dual Constraint for CMOS Cells,"
in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 74 -- 77,Apr. 2005,
- T. Yamamoto, M. Ikeda, and K. Asada,
"Symbolic Analysis of Performance Fluctuation on Analog Circuits,"
in Proc. of IEICE Karuizawa Workshop 2005, pp. 31 - 36,May 2005,
- T. Iizuka, M. Ikeda, and K. Asada,
"High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability,"
IEICE Trans. Fundamentals, Vol.E87-A, No.12, pp.3293-3300,Dec. 2004,