Y. Oike, M. Ikeda, and K. Asada,
"Design of Wide Dynamic Range Photo Detector Using Log-response and Correlation Circuit,"
DAシンポジウム2001 Prc. Of IPSJ DA Symposium, pp.159-161, Jul. 2001,
T. Nezuka, T. Fujita, M. Ikeda, and K. Asada,
"A Binary Image Sensor for Motion Detection,"
Journal of Robotics and Mechatronics, Vol.12 No.5, pp.508-514, Jun. 2001,
T. Nezuka, M. Ikeda, and K. Asada,
"A Smart Position Sensor for 3-D Measurement,"
Proceedings of JSME Conference on Robotics and Mechatronics 日本機械学会ロボティクス・メカトロニクス講演会 , 2P1-N1, May. 2001,
Y. Nakashima, M. Ikeda, and K. Asada,
"Computational Cost Reduction in Extracting Inductance,"
International Symposium on Quality Electronic Design (ISQED), Mar. 2001,
K. Asada, T. Nezuka, Y. Oike, and M. Hoshino,
(in Japanese) "3次元計測向けスマートセンサ,"
平成12年度 特定領域研究シンポジウム「知的瞬時処理複合化数隻システム」, pp.3-8, Mar. 2001,
Y. Oike, M. Ikeda, and K. Asada,
"An Image Sensor for 3-D Measurement with Correlation Technique,"
2001年電子情報通信学会総合大会, C-12-27, Mar. 2001,
K. Hoh, K. Asada, and M. Ikeda,
(in Japanese) "大規模集積システム設計教育研究センターによるVLSI設計教育・研究の支援,"
電気学会論文誌C(電子・情報・システム部門誌) Trans. IEE of Japan, Vol.121-C, No.3, pp.488-491, Mar. 2001,
S. Sugiyama, M. Ikeda, K. Asada, and H. Aoki,
"Evaluation Using Transfer Function and Analysis of Power Supply Noise,"
電子情報通信学会 VLD研究会, Mar. 2001,
T. Yamashita and K. Asada,
"Offset-Cancelling Sense Amplifier Applied with Pass-Transistor Logic ,"
電子情報通信学会論文誌 C , Vol.J84-C, No.2, pp.144-150, Feb. 2001,
T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
"A Smart Position Sensor for 3-D Measurement,"
Proceedings of ASP-DAC 2001, pp.21-22, Feb. 2001,
T. Nezuka, M. Hoshino, M. Ikeda, and K. Asada,
"A Smart Image Sensor with Quad-tree Scan,"
Journal of Image Information and Television Engineers, Vol.55, No.2, pp.287-292, Feb. 2001,
J. Qiao, M.Ikeda, and K.Asada,
"Finding an Optimal Functional Decomposition for LUT-based FPGA Syntesis,"
Asia and South Pacific Design Automation Conference 2001(ASP-DAC), Yokohama, pp.225-230, Feb. 2001,
K. Asada,
(in Japanese) "日本半導体産業の復権 2010年までの半導体技術展望 「LSI設計力の高度化」,"
電波新聞 (電波新聞社 Tel3445-8715), 2001.1.17, Jan. 2001,
T. Ishihara and K. Asada,
"A System Level Memory Power Optimization Technique Using Multiple Supply and Threshold Voltages,"
Proc. Asia and South Pacific Design Automation Conference 2001 (ASP-DAC), Yokohama, pp.456-461, Jan. 2001,
H. Yamaoka, M. Ikeda, and K. Asada,
"A High-Speed PLA using Array Logic Circuits with Latch Sense Amplifiers and a Charge Sharing Scheme,"
Proc. Asia and South Pacific Design Automation Conference 2001 (ASP-DAC), Yokohama, pp.3-4, Jan. 2001,
S. Komatsu, M. Ikeda, and K. Asada,
"Bus Data Encoding with Adaptive Code-book Method for Low Power IP Based Design ,"
International Workshop on IP-Based Synthesis and SoC Design, Dec. 2000,
H. Yamaoka, M. Ikeda, and K. Asada,
"A High-Speed PLA with Latch Sense Amplifiers,"
Proc. of 4th Workshop on System VLSI in Biwako, pp.223-226, Nov. 2000,
T. Nezuka, M. Ikeda, and K. Asada,
"A Smart Image Sensor for Position Detection with a Quad-tree Scan Controller,"
Proceedings of 4th Workshop on System VLSI in Biwako, pp.183-185, Nov. 2000,
S. Komatsu, M. Ikeda, and K. Asada,
"Data Compression Encoding Method for High Throughput Data Transmission in VLSI,"
Proc. of 4th Workshop on System VLSI in Biwako, pp.215-218, Nov. 2000,
T. Nezuka, J. Akita, M. Ikeda, and K. Asada,
"A Smart Image Sensor with Novel Implementation of Quad-tree Scan,"
Proceedings of the 2nd IEEE Asia-Pacific Conference on ASIC, pp.135-138, Oct. 2000,