Shingo Mandai


MAIN
PUBLICATION/AWARD

Technical Journal Papers
S. Manidai, T. Nakura, M. Ikeda, and K. Asada,
``Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability,''
IEICE Trans. on Electronics, Vol. E92-C, No. 6, pp. 798-805, Jun. 2009.

T. Nakura, S. Mandai, M. Ikeda, K. Asada,
``Time Difference Amplifier with Robust Gain Using Closed-Loop Control,''
IEICE Trans. on Electronics, Vol.E93-C No.3, pp.303-308, March. 2010.

S. Mandai, T. Nakura, M. Ikeda, K. Asada,
``A 8bit two stage time-to-digital converter using time difference amplifier''
IEICE Electronics Express,, vol. 7, no.13, pp. 943-948, Jul. 2010.

S. Mandai, T. Momma, M. Ikeda, and K. Asada, ``Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method,'' IEICE Trans. on Electronics, Vol. E94-C, No.1, pp. 124-127, Jan. 2011.

S. Mandai, T. Nakura, T. Iizuka, M. Ikeda, and K. Asada,
``Cascaded Time Difference Amplifier With Differential Logic Delay Cell,'' IEICE Trans. on Electronics, Vol. E94-C, No.4, pp. 654-662, Apr. 2011.

S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
``1.0ps Resolution Time-to-Digital Converter based-on Cascaded Time-Difference-Amplifier utilizing Differential Logic Delay Cells,'' IEICE Trans. on Electronics, Vol. E94-C, No.6, pp.-, Jun. 2011.

International Conference Papers
S. Mandai, T.Momma, T. Nakura, M. Ikeda, and K. Asada,
``Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip,''
in Proceedings of International SoC Design Conference(ISOCC), pp. 89-92, Nov. 2008.

S.Mandai, T.Nakura, M. Ikeda, and K. Asada,
IEEE International Solid-State Circuit Conference (ISSCC), Student Forum, Feb. 2009.

S.Mandai, T.Nakura, M. Ikeda, and K. Asada,
``Ultra High Speed 3-D Image Sensor,''
International Image Sensor Workshop(IISW), Jun. 2009.

T. Nakura, S.Mandai, M.Ikeda, and K.Asada,
``Time Difference Amplifier using Closed- Loop Gain Control,'' IEEE Symposium VLSI Circuit(VLSI Symp.) Digest of Technical Papers, pp.208-209, Jun. 2009.

S.Mandai, T.Nakura, M. Ikeda, and K. Asada,
``Cascaded Time Difference Amplifier using Differential Logic Delay Cell,''
in Proceedings of International SoC Design Conference(ISOCC), pp. 194-197, Nov. 2009.

S.Mandai, T.Nakura, M. Ikeda, and K. Asada,
``Cascaded Time Difference Amplifier using Differential Logic Delay Cell,''
in Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 355-356, Jan. 2010.

S. Mandai, M. Ikeda, and K. Asada,
``A 256 × 256 14k Range Maps/s 3-D Range-Finding Image Sensor Using Row-Parallel Embedded Binary Search Tree and Address Encoder,''
IEEE International Solid-State Circuit Conference (ISSCC) Dig. of Tech. Papers, pp.404-405, Feb. 2010.

S.Mandai, T.Nakura, M.Ikeda, and K.Asada,
``A 8bit Two Stage Time-to-Digital Con- verter Using 16x Cascaded Time Difference Amplifier in 0.18um CMOS,''
in Proceedings of IEEE Mediterranean Electrotechnical Conference(MELECON), pp.280-285, Apr. 2010.

S. Mandai, T. Iizuka, T. Nakura, M. Ikeda, and K. Asada,
``Time-to-Digital Converter Based on Time Difference Amplifier with Non-Linearity Calibration,''
IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 266-269, Sep. 2010.

S. Mandai, M. Ikeda, and K. Asada,
``High-Speed 3D Image Capture Using 1D Structured light'' IEEE International Solid-State Circuit Conference (ISSCC) Forum, Image Sensors for 3D Capture, Feb. 2011.(invited)

Technical Society Meeting and Domestic Conference Publications
S. Mandai, T. Nakura , M. Ikeda, K. Asada,
``Adaptive Row-Parallel Scan 3-D Image Sensor,''
IEICE General Conference, Mar. 2009 , (in Japanese).

S. Mandai, T. Nakura , M. Ikeda, K. Asada,
``Multi Functional Dual Imager Core Chip,''
LSI and Systems Workshop, May 2009 , (in Japanese).

S. Mandai, T. Nakura , M. Ikeda, K. Asada,
``High Resolution Time to Digital Converter using Time Difference Amplifier,''
IEICE Society Conference, Sep. 2009 , (in Japanese).

S.Mandai, T.Nakura , M.Ikeda, K.Asada,
``Cascaded Time Difference Amplifier using Differential Logic Delay Cell,”
IEICE General Conference, Mar. 2010 , (in Japanese).

S.Mandai, M.Ikeda, K.Asada,
``3-D Range-Finding Image Sensor Using Row-Parallel Embedded Binary Search Tree and Address Encoder,''
ITE Technical Report, pp.5-8, Mar. 2010 , (in Japanese).

Awards
ISOCC, IEEE CAS Seoul Chapter Best Paper Award(Oral Session), Nov. 2008.
``Multi Functional Range Finder Employing a Dual Imager Core on a Single Chip''

Excellent master thesis prize of the Department of Electrical Engineering and Information Systems, Univ. of Tokyo.
``3-D Rnage-Finding Image Sensor based on Triangulation and Time-of-Flight''

IEEE SSCS Japan Chapter Young Researcher Award,
``Is the LSI design “Omon-nai”?''

IEICE General Conference 2010, Student Award,
``Cascaded Time Difference Amplifier using Differential Logic Delay Cell''


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