- M. Sasaki, M. Ikeda, and K. Asada,
"4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-um CMOS,"
in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1007 -- 1010,Dec. 2006,
- M. Ikeda, K.H. Dia and K. Asada,
"Pre-conditioning Free Footless DCVSL for High-performance Datapaths,"
in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1053 -- 1056,Dec. 2006,
- H. Yoshida, M. Ikeda, and K. Asada,
"Exact Minimum Logic Factoring via Quantified Boolean Satisfiability,"
in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS),pp. 1065 -- 1068,Dec. 2006,
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement,"
in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 704 -- 707,Dec. 2006,(Best Student Paper Award).
- K. Asada
"CMOS Image Sensors for Smart Applications,"
the 6th Taiwan-Japan Microelectronics International Symposium, Nov.2006.
- M. Ikeda
"University-Industry Collaboration for Nanometer CMOS Design,"
the 6th Taiwan-Japan Microelectronics International Symposium, Nov.2006.
- T. Kazama, T. Nakura, M. Ikeda, and K. Asada,
"Optimization of Active Substrate Noise Cancelling Technique using Power Line di/dt Detector,"
in Proc. of IEEE Asian Solid-State Circuits Conference(A-SSCC), pp. 239 -- 242,Oct. 2006,
- K. Asada, Y. Yachide, Y. Oike, M. Ikeda
"Real-Time High-Accuracy 3-D Imaging"
in Proc. of International SoC Design Conference (ISOCC), Oct.2006.
- Y. Yachide, M. Ikeda, and K. Asada,
"Realization of Real-Time High-Accuracy Multiple-Viewpoint 3-D Imaging System,"
in Proc. of IEICE Society Conference 2006,A-1-17, p. 17,Sep. 2006, (in Japanese).
- H. Yoshida, M. Ikeda, and K. Asada,
"Synthesis of Read-Once Switch Network,"
in Proc. of IEICE Society Conference 2006,A-3-9, p. 53,Sep. 2006, (in Japanese).
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Multi-Row Transistor Placement for Dual and Non-Dual CMOS Cells,"
in Proc. of IEICE Society Conference 2006,A-3-20, p. 64,Sep. 2006, (in Japanese).
- T. Kazama, T. Nakura, M. Ikeda, and K. Asada,
"Active Substrate Noise Cancelling Method using Multiple di/dt Detectors,"
in Proc. of IEICE Society Conference 2006,C-12-22, p. 83,Sep. 2006, (in Japanese).
- K. Ishii, M. Ikeda, and K. Asada,
"Evaluation of Dual-Rail Domino Logic,"
in Proc. of IEICE Society Conference 2006,C-12-34, p. 95,Sep. 2006, (in Japanese).
- K. Asada
"CMOS Smart Image Sensor-3D HS Meas,"
IEEE 2006 VAIL Computer Elements Workshop, Jun.2006.
- T. Iizuka, M. Ikeda, and K. Asada,
"Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization,"
in Proc. of IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 884 -- 889,Mar. 2006,
- M. Abbas, M. Ikeda, and K. Asada,
"On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function,"
IEICE Trans. on Electron,Vol.E89-C, No.3, pp.370-376,Mar. 2006,
- T. Nakura, M. Ikeda, and K. Asada,
"Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply,"
IEICE Trans. on Electron, Vol.E89-C, No.3, pp.364-369,Mar. 2006,
- H. Yamauchi, M. Ikeda, K. Asada,
"Degradation of Tamper Resistant LSI by Parameter Variation of Scaled Devices and its Countermeasures,"
IEICE Technical Report, IT2005-79, pp.87-92,Mar. 2006,
- T. Iizuka, M. Ikeda, and K. Asada,
"Exact Minimum-Width Multi-Row Transistor Placement for Dual and Non-Dual CMOS Cells,"
in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5431 -- 5434,May 2006,
- T. Nakura, M. Ikeda, and K. Asada,
"On-chip di/dt Detector IP for Power Supply,"
in Proc. of IP Based SoC Design Conference & Exhibition (IP-SOC), pp.160 -- 164,Dec. 2005,