- Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada,
"Analytical Design Optimization of Sub-ranging ADC Based on Stochastic Comparator,"
IEEE/ACM Design, Automation and Test in Europe (DATE) Exhibition and Conference, Mar.2016.
- Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada,
“Performance Analysis of Analog to Digital Converter based on Stochastic Comparator(統計的コンパレータを用いたアナログ‐ディジタル変換回路の性能解析),"
IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
- Tomohiko Yano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
“A Time-Mode Analog Signal Accumulator Using a Single Buffer Ring
without Output Drift Calibration(バッファリングを利用した出力ドリフト補正が不要な時間領域
アナログ信号積分器),"
IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
- Takashi Toi, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
“Hill-Climbing法を用いたパルス幅制御PLLのPVTばらつきへの自動適応,"
IEICE Technical Committee Meeting on Integrated Circuits and Devices, Kyoto Institute of Technology,Dec.2015.
- Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno and Kunihiro Asada,
"A Technique for Analyzing On-chip Power Supply Impedance,"
Asian Test Symposium (ATS) 2015, 6B-1,Nov.2015.
- Tomohiko Yano, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
"A Calibration-Free Time Difference Accumulator Using Two Pulses Propagating on a Single Buffer Ring,"
in IEEE Asian Solid-State Circuits Conference (A-SSCC) Proceedings of Technical Papers, pp. 145-148,Nov.2015.
- T. Ikeda, M. Ikeda,
"Comprehensive Study on Higher Order Radix RSA Cryptography Engine,"
in Proceedings of the IEEE 11th International Conference on ASIC (ASICON), P2-72,Nov.2015.
- Takashi Toi, Toru Nakura, Tetsuya Iizuka and Kunihiro Asada,
"Tracking PVT variations of Pulse Width Controlled PLL using Variable-Length Ring Oscillator,"
in Proceedings of IEEE Nordic Circuits and Systems Conference(NORCAS),Oct.2015.
- Chuanqi Cui, Makoto Ikeda,
"Evaluation of SEU Tolerance of Self-synchronous System Based on Dynamic Circuits(ダイナミック回路を用いた自己同期システムの SEU 耐性の評価),"
in Proceedings of the 2015 IEICE Society Conference, A-3-9,Sep.2015.
- T. Ikeda, M. Ikeda,
"Implementation of RSA Cryptographic Circuit with High Radix Arithmetic Unit and Asynchronous Control(高基数演算器を用いたRSA暗号回路の非同期制御による実装),"
in Proceedings of the 2015 IEICE Society Conference, A-3-12,Sep.2015.
- Chuanqi Cui, M. Ikeda,
"Evaluation of SEU Tolerance of Self-synchronous System Based on Dynamic Circuits(ダイナミック回路を用いた自己同期システムの SEU 耐性の評),"
in Proceedings of the IEICE Society Conference, A-3-9,Sep.2015.
- Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
"A CMOS SPAD Sensor Featuring Asynchronous Event-Extraction Readout Architecture for Faint Light Detection,"
in Proceedings of 2015 International Conference on Solid State Devices and Materials (SSDM), pp. 812-813,Sep.2015.
- M. Kano, T. Nakura and K. Asada,
"Resonant Power Supply Noise Cancelling with Noise Detector based in DLL and Vernier TDC,"
in Proceedings of IEEE Asia Symposium on Quality Electronic Design (ASQED), pp.192-196,Aug.2015.
- Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada,
"An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors,"
in Proceedings of IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 131-136,Apr.2015.
- Xiao Yang, Hongbo Zhu, Toru Nakura, Kunihiro Asada,
"Single Photon Avalanche Diode Based on Standard CMOS Technology(標準CMOS技術による単一光子アバランシェフォトダイオード),"
in Proceedings of the 2015 IEICE General Conference, C-12-39,Mar.2015.
- K. Mori, T. Nakura, T. Iizuka, and K. Asada,
"An Accelerating Method of NBTI Degradation Transition Analysis Utilizing its Frequency Dependence(NBTIの周波数依存性を利用した劣化過渡解析の高速 化手法),"
in Proceedings of the 2015 IEICE General Conference, A-2-29,Mar.2015.
- Chuanqi Cui, M. Ikeda,
"Layout Area Estimation for Evaluation of SEU Tolerance(SEU耐性評価のためのレイアウト面積の概算),"
in Proceedings of the IEICE General Conference, C-12-25,Mar.2015.
- K. Mori, T. Nakura, T. Iizuka, and K. Asada,
"An accelerating method of NBTI degradation transition analysis based on logic simulation(論理シミュレーションにもとづいたNBTI劣化過渡解 析の高速化手法),"
ICD2014-109,CPSY2014-121, pp.141-145, Dec. 2014.
- Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada,
"A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge,"
2014 IEEE 23rd Asian Test Symposium (ATS), pp. 168-173, Nov. 2014.
- Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, and Kunihiro Asada,
"Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills,"
IEEE International Test Conference, pp. 1-10, Oct. 2014.