池野 理門 and 浅田 邦博,
"High-Speed Method for Device Simulations by Area Division,"
第59回応用物理学会学術講演会, 28pーz7ー3、pp720, Sep. 1993,
張 洪明 and 浅田 邦博,
"A Layout Method for Logic System Designed by Parthenon,"
1993年電子情報通信学会 秋季全国大会, A-68, pp.1-68, Sep. 1993,
岩崎 靖和 and 浅田 邦博,
"Numerical Analysis of Power Devices with Axially Symmetric Structure,"
第54回応用物理学会 学術講演会, 28p-ZT-8, pp.722, Sep. 1993,
池田 誠 and 浅田 邦博,
"A Design of Control Circuits for Reduced Swing Signal Data Transmission Method,"
1993年電子情報通信学会 秋季全国大会, C-441, pp.5-151, Sep. 1993,
M. Lee and K. Asada,
"A High Performance on CMOS/SOI Integrated Circuits with SIMOX Substrates,"
36th Midwest Symp. on Circuits and Systems (MWSCAS), Aug. 1993,
M. Lee, M. Fujisahima, and K. Asada,
"A High Speed and Low Power on CMOS/SOI Technology,"
51st Device Research Conference (DRC), Session ⅡA, No.8, Jun. 1993,
池田 誠 and 浅田 邦博,
"High Speed Data Transmission Method by Reduced Swing Signal for VLSI Bus Architecture,"
電子情報通信学会 技術研究報告, ED93-5D, ICD93-49 pp.39-45, Jun. 1993,
藤島 実 and 浅田 邦博,
(in Japanese) "短チャネル低電源電圧CMOS回路における負荷容量の電気的評価法,"
電子情報通信学会技術研究報告, Vol.93, No.111, pp.1-7, Jun. 1993,
張 洪明 and 浅田 邦博,
"An optimal layout method based on compatible pair search algorithm ,"
第6回回路とシステム 軽井沢ワークショップ, pp.61-65, Apr. 1993,
M. Lee, M. Fujishima, and K. Asada,
"Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
Proceedings of the 1993 IEICE Spring Conference, C-9, pp.5-203, Mar. 1993,
M. Fujishima and K. Asada,
"Proposal of Standard Characterization Method for Dynamic Circuit Performance,"
Proc. IEEE Int. Conf. on Microelectronic Test Structure , Vol.6, pp.227-232, Mar. 1993,
M. Lee, M. Fujishima, and K. Asada,
"Influence of Intrinsic and Extrinsic Capacitance on CMOS/SIMOX Inverter Delay,"
1993年電子情報通信学会 春季全国大会(IEICE), C-573, Vol.5, pp.203, Mar. 1993,
張 洪明 and 浅田 邦博,
"A Transistor pairing method for complex gate CMOS networks,"
1993年電子情報通信学会 春季全国大会, A-95, pp.1-95, Mar. 1993,
池田 誠 and 浅田 邦博,
"Reduced Voltage Bus Lines using Termination Resistors,"
1993年電子情報通信学会 春季全国大会, C-572, pp.5-202, Mar. 1993,
M. Lee and K. Asada,
"Sub-100nm CMOS/SIMOX Delay Modeling by Time-Dependent Gate Capacitance Model,"
1993 Int. Symp. on VLSI Tech., Systems, and Appl., pp.242-246, 1993,
H. Zhang and K. Asada,
"An Improved Algorithm of Transistors Pairing for Compact Layout of Non-series-parallel CMOS Networks,"
IEEE Proc. Custom Integrated Circuits Conf., pp.17.2.1-17.2.4, 1993,
張 洪明 and 浅田 邦博,
(in Japanese) "非直並列CMOS回路のレイアウト最適化手法,"
1992年電子情報通信学会 秋季全国大会, A-61, Sep. 1992,
M. Fujishima, M. Yamashita, M. Ikeda, K. Asada, Y. Omura, K. Izumi, T. Sakai, and T. Sugano,
"1GHz 50 μW 1/2 Frequency Divider Fabricated on Ultra-thin SIMOX Substrate,"
IEEE 1992 Symposium on VLSI Circuit Digest of Technical Papers, 5-4, pp.46-47, Jun. 1992,
M. Fujishima, K. Asada, T. Sasaki, M. Yamashita, Y. Omura, M. Ikeda, K. Izumi, and T. Sugano,
"1 GHz 50μ 11/8 Frequency Divider Fabricated on Ultra-thin SIMOX Substrate,"
IEEE 1992 Symposium on VLSI Circuit, Digest of Technical Papers,5-4, pp.46-47, Jun. 1992,
K. Asada, K. Ohkura, and K. R. Cho,
"Design of Self-Timed Data Path for a Fully Asynchronus Microprocessor,"
SASIMI '92, pp.HLII-1, Apr. 1992,