論文・発表リスト -- 筆頭著者分 (Published articles as the first author)



学会誌論文 (Full Paper)


Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Atsunori Hattori, Kunihiro Asada,
``Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer'',
IEICE Trans. on Electronics, Vol.E98-C, No.7 July 2015.

Toru Nakura, Hiroaki Matsui, Kunihiro Asada,
``Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guideline'',
IEICE Electronics Express, Vol.12 No.3, Feb. 2015.

Toru Nakura, Kunihiro Asada,
``Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter'',
IEICE Trans. on Electronics, Vol.E95-C No.2, pp.297-302, March. 2012.

Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada,
``Time Difference Amplifier with Robust Gain Using Closed-Loop Control'',
IEICE Trans. on Electronics, Vol.E93-C No.3, pp.303-308, March. 2010.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Autonomous di/dt Control of Power Supply for Margin Aware Operation'',
IEICE Trans. on Electronics, Vol.E89-C No.11, pp.1689-1694, Nov. 2006. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply'',
IEICE Trans. on Electronics, Vol.E89-C No.3, pp.364-369, March 2006. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs'',
IEICE Trans. on Electronics, Vol.E88-C No.8, pp.1734-1739, August 2005. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit'',
IEICE Trans. on Electronics, Vol.E88-C No.5, pp.782-787, May 2005. [PDF File]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Stub vs. Capacitor for Power Supply Noise Reduction'',
IEICE Trans. on Electronics, Vol.E88-C No.1, pp.125-132, Jan. 2005. [PDF File]

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara,
``A 3.6Gb/s 340-mW 16:1 Pipe-Lined Multiplexer using 0.18um SOI-CMOS Technology'',
IEEE Journal of Solid-State Circuits, Vol.35, No.5, pp.751-756, May 2000. [PDF File]

Toru Nakura, Yoshiaki Nakano,
``LAPAREX - An Automatic Parameter Extraction Program for Gain- and Index- Coupled Distributed Feedback Semiconductor Lasers, and Its Application to Observation of Changing Coupling Coefficients with Currents'',
IEICE Trans. on Electronics, Vol.E83-C No.3, pp.488-495, March 2000. [PDF File]




国際会議 (International Conference Presentations)


Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
``Power Supply Impedance Emulation to Eliminate Overkills and Underkills due to the Impedance Difference between ATE and Customer Board'',
IEEE International Test Conference (ITC), Sess.14-1, Nov. 2016.

Toru Nakura, Yuki Okamoto, Yoshio Mita, Kunihiro Asada
``One Week TAT of 0.8um CMOS Gate Array with Analog Elements for Educational Exercise'',
IEEE European Workshop on Microelectronics Education (EWME), Sess.6-2, May 2016.

Toru Nakura, Kunihiro Asada
``Fully Automated PLL Compiler Generating Final GDS from Specification'',
IEEE International Symbosium on Quality Electronic Design (ISQED), Sess. 6B, pp.437-442, March 2016.

Toru Nakura, Masahiro Kano, Masamitsu Yoshizawa, Seisei Oyamada, Atsunori Hattori, Kunihiro Asada
``Resonant Power Supply Noise Reduction using On-Die Decoupling Capacitors Embedded in Organic Interposer'',
IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Sess. M-III.7, Dec. 2014.

Toru Nakura, Kunihiro Asada
``Streaming Seminar: Rudimentary Knowledge for LSI Design'',
IEEE European Workshop on Microelectronics Education (EWME), Sess.4-1, May 2014.

Toru Nakura, Kunihiro Asada
``Pulse Width Controlled PLL/DLL using Soft Thermometer Code'',
IEEE Asia Solid State Circuit Conference (ASSCC), pp.345-348, Nov. 2013.

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada
``Impact of All-Digital PLL on SoC Testing'',
IEEE Asia Test Symposium (ATS), Sess7B, pp.252-257, Nov. 2012.

Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada
``7.5Vmax Arbitrary Waveform Generator with 65nm Standard CMOS under 1.2V Supply Voltage'',
IEEE Custom Integrated Circuits Conference (CICC), M-05, Sept. 2012.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Ring Oscillator Based Random Number Generator Utilizing Wake-Up Time Uncertainty'',
IEEE Asian Solid-State Circuits Conference (ASSCC), pp.121-124, Nov. 2009.

Toru Nakura, Yutaro Tatemura, Gorschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada,
``SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults'',
IEEE European Conference On Circuit Theory and Design (ECCTD), pp.643-647, Sept. 2009.

Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada,
``Time Difference Amplifier Using Closed-Loop Gain Control '',
JSAP/IEEE Symposium on VLSI Circuits, sess.20-2, pp.208-209, June 2009.

Toru Nakura, Koichi Nose, Masayuki Mizuno,
``Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops'',
International Solid-State Circuits Conference (ISSCC), pp.402-403, Feb. 2007.

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector IP for Power Supply'',
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), pp.160-164, Dec. 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Autonomous di/dt Noise Control Scheme for Margin Aware Operation '',
IMEP/LETI European Solid-State Circuit Conference (ESSCIRC), sess.8.G.2, pp.467-470, Sept. 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Feedforward Active Substrate Noise Cancelling Technique using Power Supply di/dt Detector '',
JSAP/IEEE Symposium on VLSI Circuits, sess.18-4, pp.284-287, June 2005. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Design and Measurement of On-chip di/dt Detector Circuit for Power Supply Line'',
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC) University Design Forum, sess.16-12, pp.426-427, August 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Preliminary Experiments for Power Supply Noise Reduction using Stubs'',
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), sess.13-7, pp.286-289, August 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Power Supply di/dt Measurement using On-chip di/dt Detector Circuit'',
IEEE/JSAP Symposium on VLSI Circuits, sess.7-4, pp.106-109, June 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit for Power Supply Line'',
IEEE International Conference on Microelectronic Test Structure (ICMTS), sess.1-4, pp.19-22, March 2004. [Proceeding] [Slides]

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``Theoretical Study of Stubs for Power Line Noise Reduction'',
IEEE Custom Integrated Circuits Conference (CICC), sess.31-4, pp.715-718, Sept. 2003. [Proceeding] [Slides]

Toru Nakura, Kimio Ueda, Kazuo Kubo, Warren Fernandez, Yoshio Matsuda, Koichiro Mashiko,
``A 3.6Gb/s 340-mW 16:1 Pipe-Lined Multiplexer using SOI-CMOS Technology'',
JSAP/IEEE Symposium on VLSI Circuits, sess.3-4, pp.27-31, June 1999. [Proceeding]

Toru Nakura, Kenji Sato, Masaki Funabashi, Geert Morthier, Roel Baets, Yoshiaki Nakano, Kunio Tada,
``First observation of changing coupling coefficients in a gain-coupled DFB laser with absorptive grating by automatic parameter extraction from subthreshold spectra'',
APS/IEEE/OSA Conference on Lasers and Electro-Optics (CLEO'97), CThM1, May 1997. [Proceeding]




国内会議 (Domestic Conference Presentations)


名倉 徹, 萬代 新悟, 池田 誠, 浅田邦博,
``フィードバック制御を用いた時間差増幅回路'',
電子情報通信学会研究報告集積回路研究会, ICD2009-46, pp.69-74, 2009年10月.

名倉 徹, 風間 大輔, 池田 誠, 浅田邦博,
``di/dt 検出回路を用いた基板ノイズ低減の最適化'',
電子情報通信学会研究報告集積回路研究会, ICD2007-139, pp.11-16, 2007年11月. [Proceeding] [Slides]

名倉 徹, 池田 誠, 浅田 邦博,
``LSI電源用di/dt測定回路コア'',
第7回 LSI IP デザインアワード, 2005年5月. [Proceeding] [Slides]

名倉 徹, 池田 誠, 浅田 邦博,
``オフチップスタブを用いたLSIにおける電源ノイズ低減'',
2004年電子情報通信学会ソサイエティ大会, C-12-1, pp.71, 2004年9月. [Proceeding] [Slides]

名倉 徹, 池田 誠, 浅田 邦博,
``スタブを用いた電源安定化手法'',
電子情報通信学会デザインガイア, p.217-222, 2003年11月. [Proceeding] [Slides]

名倉 徹, 廣田 尊則, 上田 公大, 益子 耕一郎, 浜野 尚徳,
``ボディ電圧制御型SOIゲートアレイを用いた0.5V 320MHz 8ビット MUX/DEMUX'',
電子情報通信学会研究報告集積回路研究会, ICD98-121, pp.67-74, 1998年8月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(IV)'',
春期第44回応用物理学関連連合講演会, 29p-PA-11, 1997年3月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの結合係数自動抽出プログラム'',
電子情報通信学会エレクトロニクスソサイエティ大会, C-315, 1996年9月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(III)'',
秋期第57回応用物理学会学術講演会, 9a-KH-4, 1996年9月. [Proceeding]

名倉 徹, 佐藤 健二, ヘールト.モルティエル, ルル.バーツ, 中野 義昭, 多田 邦雄,
``DFBレーザの閾値下スペクトルからのパラメータ抽出(II)'',
春期第43回応用物理学関連連合講演会, 27a-C-1, 1996年3月. [Proceeding]

名倉 徹, 池野 理門, 浅田 邦博,
``薄膜SOIにおけるバックゲート効果の解析モデル'',
春期第42回応用物理学関連連合講演会, 29p-K-19, 1995年3月. [Proceeding]




Invited Talk, Tutorial


Toru Nakura,
``[Invited] Time Difference Amplifier and Its Application for TDC'',
JSAP International Conference on Solid State Devices and Materials (SSDM), Sept. 2014.

Toru Nakura,
``[Invited] Numerical and Theoretical Analysis on Voltage and Time Domain Dynamic Range of scaled CMOS Circuits'',
D2T Symposium, Aug. 2014.

Toru Nakura,
``[Invited] Time Difference Amplifier and Its Application for TDC'',
IEEE SSCS UAE Chapter Seminar, Dec. 2013.

Toru Nakura,
``[Tutorial] Very Basics of IO Buffers'',
International Conference on Microelectronic Test Structures (ICMTS), March 2013.

Toru Nakura,
``[Invited] On-Chip di/dt Detector and Autonomous di/dt Noise Control for Power Supply'',
World Congress of Emerging Info Tech (WCEIT), pp.053, Aug. 2012.

Toru Nakura,
``[Invited] Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Block'',
10th Taiwan-Japan Microelectronics Symposium, Oct. 2010.

``[Panel Discussion Coordinator] Are you ready for More-than-Moore?'',
9th Japan-Taiwan Microelectronics Symposium, Sept., 2009




招待講演、チュートリアル


名倉 徹,
``[チュートリアル] 時間-デジタル変換回路(TDC)と時間差増幅回路(TDA)'',
大阪大学 先端アナログ技術セミナー, 2016年2月.

名倉 徹,
``[招待講演] LSI 設計常識講座 〜配線 RC 抽出と IO バッファ〜'',
日本学術振興会 VLSI 夏の学校, 2012年8月.

名倉 徹,
``[招待講演] 時間差増幅回路の発想から発表まで'',
電子情報通信学会研究報告集積回路研究会, ICD2010-117, pp.107-111, 2010年12月.

名倉 徹, 池田 誠, 浅田 邦博,
``[招待講演] 回路設計技術の最新動向'',
第18回エレクトロニクス実装学術講演大会, p.131-132, 2004年3月




レクチャー等


Toru Nakura,
``[Lecture] Analog+1'',
ICDREC, May. 2014.

Toru Nakura,
``[Lecture] VDEC Introduction & Low Pass Filter-less Pulse Width Controlled PLL'',
UAE Visit @ Kharifa University, Dec. 2013.

Toru Nakura,
``[Lecture] Time Difference Amplifier and Random Number Generator'',
Taiwan Visit @ National Ilan University (宣蘭大), Nov. 2009.

Toru Nakura,
``[Lecture] Time Difference Amplifier and Random Number Generator'',
Taiwan Visit @ National Don Howa University (東華大), Nov. 2009.




受賞 (Award)


Toru Nakura, Kunihiro Asada,
``Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter'',
IEICE Trans. on Electronics, Vol.E95-C No.2, pp.297-302, March 2012.
電子情報通信学会 平成 24 年度 論文賞

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector IP for Power Supply'',
IP Based SoC Design Conference & Exhibition (IP-SOC 2005), pp.160-164, Dec. 2005.
Best Paper Award

名倉 徹, 池田 誠, 浅田 邦博,
``LSI 電源用 di/dt 測定回路コア'',
第 7 回 LSI IP デザインアワード, 3 月, 2010
IP 優秀賞

Toru Nakura, Makoto Ikeda, Kunihiro Asada,
``On-chip di/dt Detector Circuit'',
IEICE Trans. on Electronics, Vol.E88-C No.5, pp.782-787, May 2005.
電子情報通信学会 平成 17 年度 論文賞




International or US Patents


Toru Nakura, Kunihiro Asada,
``Signal Conversion Circuit, PLL Circuit, Delay Adjustment Circuit, and Phase Control Circuit'',
PCT/JP2012/063206

Toru Nakura, Masayuki Mizuno, Koichi Nose,
``Failure Prediction Circuit and Method, and Semiconductor Integrated Circuit'',
US 2010/0251046 A1, September 30, 2010 (USA)

Toru Nakura, Kmio Ueda,
``Fast operating multiplexer'',
6477186, November 5, 2002 (USA)

Toru Nakura, Kmio Ueda,
``Semiconductor device with reduced transistor leakage current'',
6472712, October 29, 2002 (USA)

Toru Nakura, Kmio Ueda,
``Synchronous frequency dividing circuit'',
6249157, June 19, 2001 (USA)

Toru Nakura, Kmio Ueda,
``Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing varous types of surge'',
6208494, March 27, 2001 (USA)

Toru Nakura, Kmio Ueda,
``Counter circuit'',
6101233, August 8, 2000 (USA)




国内特許


名倉 徹, 浅田 邦博,
``信号変換回路、PLL 回路、遅延調整回路及び位相制御回路'',
PCT/JP2012/063206

名倉 徹, 浅田 邦博, 飯塚 哲也, 久保田 透
``光子検出装置および放射線測定装置'',
特開2014-215145, 2008年8月

名倉 徹, 浅田 邦博,
``信号変換回路、PLL 回路、遅延調整回路及び位相制御回路'',
PCT/JP2012/06320

名倉 徹, 水野 正之, 野瀬 浩一,
``故障予測回路と方法及び半導体集積回路'',
再公開08-023577, 2008年2月

名倉 徹, 野瀬 浩一, 水野 正之, 池田 誠, 浅田 邦博,
``半導体集積回路及び動作条件制御方法'',
特開2008-192040, 2008年8月

名倉 徹, 上田 公大,
``マルチプレクサ'',
特開2000-278141, 2000年12月

名倉 徹, 上田 公大,
``分周回路'',
特開2000-224026, 2000年8月

名倉 徹, 上田 公大,
``半導体装置およびその製造方法'',
特開2000-223701, 2000年8月

名倉 徹, 上田 公大,
``半導体集積回路装置'',
特開2000-012788, 2000年1月

名倉 徹, 上田 公大,
``カウンタ回路'',
特開平11-330951, 1999年11月

詳しい内容は、特許庁ホームページの 特許電子図書館/特許・実用検索/公報テキスト検索/ にて"発明者"を選択して"名倉徹"で検索してください。アメリカの特許は、United States Patent and Trademark Office ホームページの Patents/Services/SEARCH patents/Quick Search/ にて "Nakura" in Field "Inventor Name" で検索してください。



卒業論文・修士論文・博士論文 (Bachelor, Master and Ph.D Thesis)


Toru Nakura, (Superviser) Kunihiro Asada,
``A Study on Power Line Noise Reduction in Large Scale Integration'',
For the degree of Doctor of Philosophy, Department of Electronic Engineering, the University of Tokyo, December 2004. [Paper] [Handout] [Slides]

名倉 徹, (指導教官) 中野 義昭,
``分布帰還型半導体レーザにおける閾値下スペクトルからのパラメータ抽出'',
東京大学大学院工学系研究科電子工学専攻 修士論文, 1997年2月 [PDF File]

名倉 徹, (指導教官) 浅田 邦博,
``薄膜SOIにおけるバックゲート効果'',
東京大学工学部電子工学科 卒業論文, 1995年2月 [PDF File]


著書


アナログ RF CMOS 集積回路設計 応用編 [培風館] (第 12 章, 第 13 章, 第 22 章)
LSI 設計常識講座 [東京大学出版会]
Essential Knowledge for Transistor-Level LSI Circuit Design [Springer]

起業


株式会社アイカデザイン設立 (2013年)

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